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參數(shù)資料
| 型號(hào)： | celeron cpu Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器1（MMC管理- 1）在466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器1處理器） |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 448K |
| 代理商： | CELERON CPU MOBILE MODULE |
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8
Celeron
Processor Mobile Module MMC-1
at 466 MHz and 433 MHz
3.1.5
Power Management (8 Signals)
Table 5 lists the power management interface signals. The
SM_CLK and SM_DATA signals refer to the two-wire serial
SMBus interface. Although this interface is currently used
solely for the digital thermal sensor, the SMBus contains
reserved serial addresses for future use. See section 4.9 for
more details.
Table 5. Power Management Signal Descriptions
Voltage
Name
Type
Description
OEM_PU
I
CMOS
N/C
CMOS
I
CMOS
I
V_3
OEM Pullup:
This pullup resistor is not required on the Celeron processor mobile
module MMC-1.
L2_ZZ
V_CPUIO
Low-Power Mode For Cache SRAM:
This signal is not used on the Celeron
processor mobile module MMC-1.
SUS_STAT#
V_3ALWAYS
1
Suspend Status:
This signal connects to the SUS_STAT1# outputs of PIIX4E/M. It
provides information on host clock status and is asserted during all suspend states.
VR_ON
V_3
VR_ON:
Voltage regulator ON.
This 3.3V (5V tolerant) signal controls the operation
of the voltage regulator.
VR_ON should be generated as a function of the PIIX4E/M
SUSB# signal, which is used for controlling the “Suspend State B” voltage planes.
This signal should be driven by a digital signal with a rise/fall time of less than or
equal to 1 us. (VIL(max)=0.4V, VIH(min)=3.0V). See Figure 5, “Power-on Sequence
Timing” for proper sequencing of VR_ON.
VR_PWRGD
O
V_3
VR_PWRGD:
This signal is driven high to indicate that the voltage regulator is
stable and is pulled low using a 100K resistor when inactive.
It can be used in some
combination to generate the system PWRGOOD signal.
SM_CLK
I/O D
CMOS
V_3
Serial Clock:
This clock signal is used on the SMBus interface to the digital thermal
sensor. Ensure proper termination based upon the
System Management Bus
Specification, Revision 1.0
.
SM_DATA
I/O D
CMOS
V_3
Serial Data:
An open-drain data signal on the SMBus interface to the digital thermal
sensor. Ensure proper termination based upon the
System Management Bus
Specification, Revision 1.0
.
ATF_INT#
O D
CMOS
V_3
ATF Interrupt:
This signal is an open-drain output signal of the digital thermal
sensor.
NOTE:
V_3ALWAYS: 3.3V supply. It is generated whenever V_DC is available and supplied to PIIX4E/M resume well.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
| CEM2005 | Dual Enhancement Mode Field Effect Transistor(N and Channel) |
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| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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