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參數(shù)資料
| 型號(hào)： | celeron cpu Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器1（MMC管理- 1）在466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器1處理器） |
| 文件頁數(shù)： | 20/42頁 |
| 文件大?。?/td> | 448K |
| 代理商： | CELERON CPU MOBILE MODULE |
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16
Celeron
Processor Mobile Module MMC-1
at 466 MHz and 433 MHz
Table 12. Configuration Straps for the 82443DX Host Bridge System Controller
Signal
Function
Module Default Setting
MAB[12]#
Host Frequency
Select
No strap
66-MHz default.
MAB[11]#
In order queue depth
No strap
maximum queue depth is set, i.e. 8.
MAB[10]
Quick Start select
Strapped high on the module for Quick Start mode.
MAB[9]#
AGP disable
Strapped to disable AGP.
MAB[7]#
MM Config
Strapped for MMC-1 compatible mode.
MAB[6]#
Host Bus Buffer Mode
select
Strapped high on the module for mobile PSB buffers.
4.3.3
PCI Interface
The PCI interface of the 82443DX Host Bridge is available at
the connector. The 82443DX Host Bridge supports the PCI
Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain
signal when they require the use of the PCI interface. Refer
to the
PCI Mobile Design Guide
for complete details on the
PCI Clockrun protocol.
The 82443DX Host Bridge is responsible for arbitrating the
PCI bus. With the MMC-1 connector the 82443DX Host
Bridge can support up to five PCI bus masters. There are
five PCI Request/Grant pairs, REQ[4:0]# and GNT[4:0]#,
available to the manufacturer’s system electronics.
The PCI interface on the connector is 3.3 volts only. All
devices that drive outputs to a 5.0
Vt
nominal V
oh
level are not
supported.
The 82443DX Host Bridge system controller is compliant
with the PCI 2.1 specification, which improves the worst
case PCI bus access latency from earlier PCI specifications.
As detailed in the PCI specification, the 82443DX Host
Bridge supports only Mechanism #1 for accessing PCI
configuration space. This implies that signals AD[31:11] are
available for PCI IDSEL signals. However, since the
82443DX Host Bridge is always device #0, AD11 will never
be asserted during PCI configuration cycles as an IDSEL.
The 82443DX reserves AD12 for the AGPbus, which is not
supported by the MMC-1 connector. Thus, AD13 is the first
available address line usable as an IDSEL. AD18 should be
used by the PIIX4E/M.
4.3.4
AGP Feature Set
The Intel MMC-1 family does not support the AGP graphics
port interface. For AGP information, refer to the
Intel
a
Celeron
Processor Mobile Module: Mobile Module
Connector 2 (MMC-2).
4.4
Power Management
4.4.1
Clock Control Architecture
The Celeron processor mobile module’s clock control
architecture is optimal for notebook designs. The clock
control architecture consists of seven different clock states:
Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant
Snoop, Sleep, and Deep Sleep. The Auto Halt state provides
a low power clock state that can be controlled through the
software execution of the HLT instruction. The Quick Start
state provides a low power, low exit latency clock state that
can be used for hardware controlled “idle” computer states.
The Deep Sleep state provides an extremely low power state
that can be used for “Power-on Suspend” states, which is an
alternative to shutting off the processor’s power.
The exit latency of the Deep Sleep state has been reduced
to 30 microseconds. The Stop Grant and Sleep states are
not available on the Celeron processor mobile module as
these states are intended for desktop or server systems. The
Stop Grant and the Quick Start clock states are mutually
exclusive. For example a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is
asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the
STPCLK# signal puts the mobile Celeron processor into the
Stop Grant state. The Stop Grant state is useful for SMP
platforms and is not supported on the Celeron processor
mobile module MMC-1. The Quick Start state is available on
the module and provides a significantly lower power level.
Figure 3 provides an illustration of the clocking architecture.
Performing state transitions not shown in Figure 3 is neither
recommended nor supported.
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
| CEM2005 | Dual Enhancement Mode Field Effect Transistor(N and Channel) |
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