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參數(shù)資料
| 型號(hào)： | celeron cpu Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器1（MMC管理- 1）在466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器1處理器） |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 448K |
| 代理商： | CELERON CPU MOBILE MODULE |
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15
Celeron
Processor Mobile Module MMC-1
at 466 MHz and 433 MHz
Table 11 summarizes the key specifications for the MMC-1 connector.
Table 11. Connector Specifications
Condition
Parameter
Specification
Material
Contact
Copper Alloy
Housing
Thermo Plastic Molded Compound: LCP
Electrical
Current
0.5 A
Voltage
50 VAC
Insulation Resistance
100 M
minimum at 200 VDC
Termination Resistance
50 m
maximum
Capacitance
5 pF maximum per contact
Mechanical
Mating Cycles
50 cycles
Connector Mating Force
3.2 oz per contact
Contact Unmating Force
0.35 oz per contact
4.0
FUNCTIONAL DESCRIPTION
4.1
Celeron Processor Mobile Module MMC-1
The Celeron processor mobile module MMC-1 is offered at
speeds of 466 megahertz and 433 megahertz. All processor
speeds have a PSB speed of 66 megahertz.
4.2
L2 Cache
The on-die L2 cache is 128 kilobytes, is four-way set
associative, and runs at the speed of the processor core.
4.3
The 82443DX Host Bridge System
Controller
Intel’s 82443DX Host Bridge system controller combines the
mobile Celeron processor bus controller, the DRAM
controller, and the PCI bus controller into one component.
The 82443DX Host Bridge has multiple power management
features designed specifically for notebook systems such as:
CLKRUN#, a feature that enables controlling of the PCI
clock on or off.
The 82443DX Host Bridge suspend modes, which
include Suspend-to-RAM (STR), Suspend-to-Disk
(STD), and Powered-On-Suspend (POS).
System Management RAM (SMRAM) power
management modes, which include Compatible
SMRAM (C_SMRAM) and Extended SMRAM
(E_SMRAM). C_SMRAM is the traditional SMRAM
feature implemented in all Intel PCI chipsets.
E_SMRAM is a new feature that supports write-back
cacheable SMRAM space up to 1 megabyte. To
minimize power consumption while the system is idle,
the internal 82443DX Host Bridge clock is turned off
(gated off). This is accomplished by setting the G_CLK
enable bit in the power management register in the
82443DX through the system BIOS.
4.3.1
Memory Organization
The MMC-1 connector signaling interface supports the
82443DX Host Bridge standard mode, memory
configurations, and modes of operation. This allows the
memory interface to support the following:
One set of memory control signals, sufficient to support
up to three SO-DIMM sockets and six banks of SDRAM
at 66 megahertz.
One CKE signal for each bank.
Memory features not supported by the 82443DX Host Bridge
system controller standard MMC-1 mode are:
Support for eight banks of memory.
Second set of memory address lines (MAA[13:0]).
Accelerated Graphics Port (AGP).
The 82443DX Host Bridge system controller supports DRAM
technologies EDO and SDRAM. These memory types should
not be mixed in the system, so that all DRAM in all rows
(RAS[5:0]#) must be of the same technology. The 82443DX
Host Bridge system controller targets 60-nanosecond EDO
DRAMs, and 66-megahertz SDRAMs.
The Celeron processor mobile module’s clocking
architecture supports the use of SDRAM. Tight timing
requirements of the 66-megahertz SDRAM clocks allow all
host and SDRAM clocks to be generated from the same
clocking architecture on the OEM’s system electronics. For
complete details about using SDRAM memory and for trace
length guidelines, refer to the
Mobile Pentium II processor /
82443BX PCIset Advanced Platform Recommended Design
and Debug Practices.
Refer to the
Intel
a
440BX PCIset
Datasheet
for details on memory device support,
organization, size, and addressing.
4.3.2
Reset Strap Options
Several strap options on the memory address bus define the
behavior of the Celeron processor mobile module
MMC-1after reset. Other straps are allowed to override the
default settings. Table 14 shows the various straps and their
implementation.
相關(guān)PDF資料 |
PDF描述 |
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| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
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| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
| CEM2005 | Dual Enhancement Mode Field Effect Transistor(N and Channel) |
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