參數(shù)資料
型號: CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 64/90頁
文件大小: 1560K
代理商: CDB42528
CS42526
64
DS585PP5
6.20.4 D TO E U-BUFFER TRANSFER (DETU)
Default = 0
Function:
Indicates when the user status buffer has changed.
6.20.5 ADC OVERFLOW (OVERFLOW)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42526 ADC signal path.
6.20.6 RECEIVER ERROR (RERR)
Default = 0
Function:
Indicates that a receiver error has occurred. The register “Receiver Errors (address 26h) (Read Only)”
on page 67 may be read to determine the nature of the error which caused the interrupt.
6.21
Interrupt Mask (address 21h)
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status
(address 20h) (Read Only)” on page 63. If a mask bit is set to 1, the error is unmasked, meaning that
its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is
masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions
align with the corresponding bits in the Interrupt Status register.
6.22
Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)
Default = 00000000
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There
are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active
level(Active High or Low) only depends on the INT(1:0) bits located in the register “Receiver Mode
Control (address 1Eh)” on page 61.
00 - Rising edge active
7
6
5
4
3
2
1
0
UNLOCKM
Reserved
QCHM
DETCM
DETUM
Reserved
OverFlowM
RERRM
7
6
5
4
3
2
1
0
UNLOCK1
UNLOCK0
Reserved
Reserved
QCH1
QCH0
DETC1
DETC0
DETU1
DETU0
Reserved
Reserved
OF1
OF0
RERR1
RERR0
相關(guān)PDF資料
PDF描述
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
CDB4271 24-Bit, 192 kHz Stereo Audio CODEC
CDB4272 24-Bit, 192 kHz Stereo Audio CODEC
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CDB42L50 Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:No RoHS Compliant: No
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