參數(shù)資料
型號: CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 61/90頁
文件大?。?/td> 1560K
代理商: CDB42528
DS585PP5
61
CS42526
6.16
ADC Left Channel Gain (address 1Ch)
6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
6.17
ADC Right Channel Gain (address 1Dh)
6.17.1 ADC RIGHT CHANNEL GAIN (RGAINX)
Default = 00h
Function:
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
6.18
Receiver Mode Control (address 1Eh)
6.18.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
Default = 0
0 - CX & SAI Serial Port timings not in phase
1 - CX & SAI Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the
CX & SAI
Serial Ports to align and operate in phase. This func-
tion will operate when both ports are running at the same sample rate or when operating at different
sample rates.
7
6
5
4
3
2
1
0
Reserved
Reserved
LGAIN5
LGAIN4
LGAIN3
LGAIN2
LGAIN1
LGAIN0
7
6
5
4
3
2
1
0
Reserved
Reserved
RGAIN5
RGAIN4
RGAIN3
RGAIN2
RGAIN1
RGAIN0
Binary Code
001111
001010
000101
000000
111011
110110
110001
Decimal Value
+15
+10
+5
0
-5
-10
-15
Volume Setting
+15 dB
+10 dB
+5 dB
0 dB
-5 dB
-10 dB
-15 dB
Table 17. Example ADC Input Gain Settings
7
6
5
4
3
2
1
0
SP_SYNC
Reserved
DE-EMPH1
DE-EMPH0
INT1
INT0
HOLD1
HOLD0
相關(guān)PDF資料
PDF描述
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
CDB4271 24-Bit, 192 kHz Stereo Audio CODEC
CDB4272 24-Bit, 192 kHz Stereo Audio CODEC
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