參數(shù)資料
型號(hào)： CDB42528
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述： 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁(yè)數(shù)： 4/90頁(yè)
文件大小： 1560K
代理商： CDB42528
CS42526
4
DS585PP5
12.1 External Filter Components ...........................................................................................80
12.1.1 General .............................................................................................................80
12.1.2 Jitter Attenuation ...............................................................................................80
12.1.3 Capacitor Selection ...........................................................................................81
12.1.4 Circuit Board Layout ..........................................................................................81
13. APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ..............82
13.1 AES3 Receiver External Components ...........................................................................82
14. APPENDIX E: ADC FILTER PLOTS ....................................................................................83
15. APPENDIX F: DAC FILTER PLOTS ....................................................................................85
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing ..........................................................................12
Figure 2. Serial Audio Port Slave Mode Timing ............................................................................12
Figure 3. Control Port Timing - I
2
C Format ...................................................................................13
Figure 4. Control Port Timing - SPI Format...................................................................................14
Figure 5. Typical Connection Diagram..........................................................................................20
Figure 6. Full-Scale Analog Input..................................................................................................21
Figure 7. Full-Scale Output ...........................................................................................................22
Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ........................................................23
Figure 9. CS42526 Clock Generation ...........................................................................................25
Figure 10. I
2
S Serial Audio Formats..............................................................................................29
Figure 11. Left Justified Serial Audio Formats ..............................................................................30
Figure 12. Right Justified Serial Audio Formats............................................................................30
Figure 13. One Line Mode #1 Serial Audio Format.......................................................................31
Figure 14. One Line Mode #2 Serial Audio Format.......................................................................31
Figure 15. ADCIN1/ADCIN2 Serial Audio Format.........................................................................32
Figure 16. OLM Configuration #1..................................................................................................33
Figure 17. OLM Configuration #2..................................................................................................34
Figure 18. OLM Configuration #3..................................................................................................35
Figure 19. OLM Configuration #4..................................................................................................36
Figure 20. OLM Configuration #5..................................................................................................37
Figure 21. Control Port Timing in SPI Mode..................................................................................38
Figure 22. Control Port Timing, I
2
C Write......................................................................................39
Figure 23. Control Port Timing, I
2
C Read .....................................................................................39
Figure 24. Recommended Analog Input Buffer.............................................................................75
Figure 25. Recommended Analog Output Buffer..........................................................................75
Figure 26. Channel Status Data Buffer Structure..........................................................................77
Figure 27. PLL Block Diagram ......................................................................................................79
Figure 28. Jitter Attenuation Characteristics of PLL......................................................................80
Figure 29. Recommended Layout Example..................................................................................81
Figure 30. Consumer Input Circuit ................................................................................................82
Figure 31. S/PDIF MUX Input Circuit ............................................................................................82
Figure 32. TTL/CMOS Input Circuit...............................................................................................82
Figure 33. Single Speed Mode Stopband Rejection .....................................................................83
Figure 34. Single Speed Mode Transition Band............................................................................83
Figure 35. Single Speed Mode Transition Band (Detail)...............................................................83
Figure 36. Single Speed Mode Passband Ripple..........................................................................83
Figure 37. Double Speed Mode Stopband Rejection....................................................................83
Figure 38. Double Speed Mode Transition Band..........................................................................83
Figure 39. Double Speed Mode Transition Band (Detail)..............................................................84
Figure 40. Double Speed Mode Passband Ripple........................................................................84
Figure 41. Quad Speed Mode Stopband Rejection.......................................................................84
Figure 42. Quad Speed Mode Transition Band.............................................................................84
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