參數(shù)資料
型號(hào): CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 46/90頁
文件大?。?/td> 1560K
代理商: CDB42528
CS42526
46
DS585PP5
6. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, In-
terrupt Status Register, and Q-Channel Subcode Bytes and C-bit or U-bit Data Buffer, which are read
only. See the following bit definition tables for bit assignment information. The default state of each bit
after a power-up sequence or reset is listed in each bit description.
6.1
Memory Address Pointer (MAP)
Not a register
6.1.1
INCREMENT(INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
6.1.2
MEMORY ADDRESS POINTER (MAPX)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control
port.
6.2
Chip I.D. and Revision Register (address 01h) (Read Only)
6.2.1
CHIP I.D. (CHIP_IDX)
Default = 1111
Function:
I.D. code for the CS42526. Permanently set to 1111.
6.2.2
CHIP REVISION (REV_IDX)
Default = 0100
Function:
CS42526 revision level.
Revision D is coded as 0100.
Revision C is coded as 0011.
7
6
5
4
3
2
1
0
INCR
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
7
6
5
4
3
2
1
0
Chip_ID3
Chip_ID2
Chip_ID1
CHIP_ID0
Rev_ID3
Rev_ID2
Rev_ID1
Rev_ID0
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