參數(shù)資料
型號: CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 89/90頁
文件大?。?/td> 1560K
代理商: CDB42528
DS585PP5
89
CS42526
Table 22. Revision History
Release
A1
PP1
PP2
Date
Changes
December 2002
August 2003
August 2003
Advance Release
Preliminary Release
– Added Revision History table.
– Updated registers 6.7.4 and 6.7.5 on page 53.
Corrected error in document title.
Add lead free part numbers
– Updated PLL components in Table 21 on page 80.
– Added PDN_RCVR1 bit and description on page 47.
Added LOCKM bit and description on page 65.
Added OMCK Frequency specification in the Switching Characteristics table on
page 12.
Updated ADC Input Impedance and Offset Error specifications in the Analog
Input Characteristics table on page 8.
Updated the DAC Full Scale Voltage, Output Impedance, and Gain Drift
specifications in the Analog Output Characteristics table on page 10.
Updated specification conditions for the analog input characteristics on page 8.
Updated specification conditions for the analog output characteristics on
page 10.
Updated specification of t
ds
and t
dh
in the Switching Characteristics table on
page 12.
Corrected reference to the SW_CTRL[1:0] bits in section 4.5.3 on page 26.
Moved the VQ and FILT+ specifications from the Analog Input Characteristics
table on page 8 to the DC Electrical Characteristics table on page 15.
– Updated the Power Supply Current and Power Consumption specifications in
the DC Electrical Characteristics table on page 15.
– Updated the description of the CONF bit on page page 67.
– Updated Table 13 on page 54 to include HDCD format detection.
– Corrected default value of the Chip_ID[3:0] bits in register 01h on pages 42 and
46.
– Updated default value of the Rev_ID[3:0] bits in register 01h on pages 42 and
46.
PP3
PP4
PP5
March 2004
July 2004
January 2005
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PDF描述
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
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