參數(shù)資料
型號(hào): CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 6/90頁
文件大?。?/td> 1560K
代理商: CDB42528
CS42526
6
DS585PP5
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies...............................................................................26
Table 2. Common PLL Output Clock Frequencies........................................................................26
Table 3. Slave Mode Clock Ratios................................................................................................26
Table 4. Serial Audio Port Channel Allocations.............................................................................27
Table 5. DAC De-Emphasis..........................................................................................................49
Table 6. Receiver De-Emphasis....................................................................................................49
Table 7. Digital Interface Formats.................................................................................................50
Table 8. ADC One-Line Mode.......................................................................................................50
Table 9. DAC One-Line Mode.......................................................................................................50
Table 10. RMCK Divider Settings..................................................................................................52
Table 11. OMCK Frequency Settings............................................................................................53
Table 12. Master Clock Source Select..........................................................................................53
Table 13. AES Format Detection...................................................................................................54
Table 14. Receiver Clock Frequency Detection............................................................................55
Table 15. Example Digital Volume Settings..................................................................................58
Table 16. ATAPI Decode...............................................................................................................60
Table 17. Example ADC Input Gain Settings................................................................................61
Table 18. TXP Output Selection....................................................................................................62
Table 19. Receiver Input Selection ...............................................................................................63
Table 20. Auxiliary Data Width Selection......................................................................................66
Table 21. PLL External Component Values..................................................................................80
Table 22. Revision History ..........................................................................................................89
相關(guān)PDF資料
PDF描述
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
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