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參數(shù)資料
| 型號： | CDB42528 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver |
| 中文描述： | 114分貝192千赫6通道編解碼器與S / PDIF接收器 |
| 文件頁數(shù)： | 27/90頁 |
| 文件大?。?/td> | 1560K |
| 代理商： | CDB42528 |
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DS585PP5
27
CS42526
4.6
4.6.1
The CS42526 interfaces to an external Digital Audio Processor via two independent serial ports, the
CODEC serial port, CODEC_SP and the Serial Audio Interface serial port, SAI_SP. The digital output of
the internal ADCs can be configured to use either the CX_SDOUT pin or the SAI_SDOUT pin and the
corresponding serial port clocking signals. These configuration bits and the selection of Single, Double or
Quad-Speed mode for CODEC_SP and SAI_SP are found in register “Functional Mode (address 03h)”
on page 48.
The serial interface clocks, SAI_SCLK for SAI_SP and CX_SCLK for CODEC_SP, are used for transmit-
ting and receiving audio data. Either SAI_SCLK or CX_SCLK can be generated by the CS42526 (master
mode) or it can be input from an external source (slave mode). Master or Slave mode selection is made
using bits CODEC_SP M/S and SAI_SP M/S in register “Misc Control (address 05h)” on page 51.
The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start
of a new sample period. It may be an output of the CS42526 (master mode), or it may be generated by
an external source (slave mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each
other.
The serial data interface format selection (left/right justified, I
2
S or one line mode) for the Serial Audio In-
terface serial port data out pin, SAI_SDOUT, the CODEC serial port data out pin, CX_SDOUT, and the
CODEC input pins, CX_SDIN1:3, is configured using the appropriate bits in the register “Interface For-
mats (address 04h)” on page 49. The serial audio data is presented in 2's complement binary form with
the MSB first in all formats.
CX_SDIN1, CX_SDIN2, and CX_SDIN3 are the serial data input pins supplying the associated internal
DAC. CX_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when
configured for one-line mode, up to four additional ADC channels attached externally to the signals
ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One Line Mode, 6 channels
of DAC data are input on CX_SDIN1 and 6 channels of ADC data are output on CX_SDOUT. Table 4
outlines the serial port channel allocations.
Digital Interfaces
Serial Audio Interface Signals
SCLK/LRCK Ratio
32x, 48x, 64x, 128x
32x, 48x, 64x
32x, 48x, 64x
128x
Serial Inputs / Outputs
CX_SDIN1 left channel
right channel
one line mode
CX_SDIN2 left channel
right channel
one line mode
CX_SDIN3 left channel
right channel
one line mode
DAC #1
DAC #2
DAC channels 1,2,3,4,5,6
DAC #3
DAC #4
not used
DAC #5
DAC #6
not used
Table 4. Serial Audio Port Channel Allocations
Single Speed
Double Speed
Quad Speed
One Line Mode #1
Table 3. Slave Mode Clock Ratios
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| CDB4265 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4270 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 105dB 192kHz CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4271 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd CS4271 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4272 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd CS4272 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4299 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd AC’97 CODEC w/SRC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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