參數(shù)資料
型號(hào)： CDB42528
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述： 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁(yè)數(shù)： 3/90頁(yè)
文件大?。?/td> 1560K
代理商： CDB42528
DS585PP5
3
CS42526
5. REGISTER QUICK REFERENCE .......................................................................................... 42
6. REGISTER DESCRIPTION .................................................................................................... 46
6.1 Memory Address Pointer (MAP)....................................................................................... 46
6.2 Chip I.D. and Revision Register (address 01h) (Read Only)............................................ 46
6.3 Power Control (address 02h)............................................................................................ 47
6.4 Functional Mode (address 03h)........................................................................................ 48
6.5 Interface Formats (address 04h) ...................................................................................... 49
6.6 Misc Control (address 05h) .............................................................................................. 51
6.7 Clock Control (address 06h)............................................................................................. 52
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 54
6.9 RVCR Status (address 08h) (Read Only)......................................................................... 54
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only).......................... 55
6.11 Volume Transition Control (address 0Dh) ...................................................................... 56
6.12 Channel Mute (address 0Eh).......................................................................................... 58
6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ........................................ 58
6.14 Channel Invert (address 17h)......................................................................................... 58
6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)............................................. 59
6.16 ADC Left Channel Gain (address 1Ch) .......................................................................... 61
6.17 ADC Right Channel Gain (address 1Dh)........................................................................ 61
6.18 Receiver Mode Control (address 1Eh) ........................................................................... 61
6.19 Receiver Mode Control 2 (address 1Fh) ........................................................................ 62
6.20 Interrupt Status (address 20h) (Read Only) ................................................................... 63
6.21 Interrupt Mask (address 21h) ......................................................................................... 64
6.22 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)................................................................................ 64
6.23 Channel Status Data Buffer Control (address 24h)........................................................ 65
6.24 Receiver Channel Status (address 25h) (Read Only) .................................................... 66
6.25 Receiver Errors (address 26h) (Read Only)................................................................... 67
6.26 Receiver Errors Mask (address 27h).............................................................................. 68
6.27 MuteC Pin Control (address 28h)................................................................................... 68
6.28 RXP/General Purpose Pin Control (addresses 29h to 2Fh)........................................... 69
6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only)......................... 71
6.30 C-bit or U-bit Data Buffer (addresses 3Ah to 51h) (Read Only) ..................................... 71
7. PARAMETER DEFINITIONS .................................................................................................. 72
8. REFERENCES ........................................................................................................................ 73
9. PACKAGE DIMENSIONS ................................................................................................... 74
THERMAL CHARACTERISTICS ........................................................................................... 74
10. APPENDIX A: EXTERNAL FILTERS ................................................................................... 75
10.1 ADC Input Filter ............................................................................................................. 75
10.2 DAC Output Filter .......................................................................................................... 75
11. APPENDIX B: S/PDIF RECEIVER ....................................................................................... 76
11.1 Error Reporting and Hold Function ................................................................................ 76
11.2 Channel Status Data Handling ...................................................................................... 76
11.2.1 Channel Status Data E Buffer Access .............................................................. 77
11.2.1a One Byte mode .................................................................................. 77
11.2.1b Two Byte mode .................................................................................. 77
11.2.2 Serial Copy Management System (SCMS) ....................................................... 78
11.3 User (U) Data E Buffer Access ...................................................................................... 78
11.3.1 Non-Audio Auto-Detection ................................................................................ 78
11.3.1a Format Detection ............................................................................... 78
12. APPENDIX C: PLL FILTER .................................................................................................. 79
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