參數(shù)資料
型號(hào): CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁(yè)數(shù): 70/90頁(yè)
文件大?。?/td> 1560K
代理商: CDB42528
CS42526
70
DS585PP5
ignored. It is recommended that in this mode this bit be set to 0.
6.28.3 FUNCTIONAL CONTROL (FUNCTIONX)
Default = 00000
Function:
RXP Input - If the pin is configured for an RXP input, the functional bits are ignored. It is recommended
that in this mode all the functional bits be set to 0.
Mute Mode - If the pin is configured as a dedicated mute pin, then the functional bits determine which
channel mutes will be mapped to this pin according to the following table.
0 - Channel mute is not mapped to the RXPx/GPOx pin
1 - Channel mute is mapped to the RXPx/GPOx pin:
GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow
Mode pin, then the Function1 and Function0 bits determine how the output will behave according to
the following table. It is recommended that in this mode the remaining functional bits be set to 0.
GPO, Drive High - If the pin is configured as a general purpose output, then the functional bits are
ignored and the pin is driven high. It is recommended that in this mode all the functional bits be set to
0.
RXPx/GPOx
RXP7/GPO7
pin 42
RXP6/GPO6
pin 43
RXP5/GPO5
pin 44
RXP4/GPO4
pin 45
RXP3/GPO3
pin 46
RXP2/GPO2
pin 47
RXP1/GPO1
pin 48
Reg Address
29h
Function4
M_AOUTA1
Function3
M_AOUTB1
Function2
M_AOUTA2
M_AOUTB2
M_AOUTB2
Function1
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
M_AOUTB3
Function0
Reserved
2Ah
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA2
Reserved
2Bh
M_AOUTA2
M_AOUTB2
Reserved
2Ch
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA3
Reserved
2Dh
M_AOUTA3
M_AOUTB3
Reserved
2Eh
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
Reserved
Reserved
2Fh
Reserved
Reserved
Function1
0
1
Function0
0
1
GPOx
Drive Low
OVFL R or L
Driver Type
CMOS
Open Drain
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