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參數(shù)資料
| 型號： | CDB42528 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver |
| 中文描述： | 114分貝192千赫6通道編解碼器與S / PDIF接收器 |
| 文件頁數(shù)： | 52/90頁 |
| 文件大小： | 1560K |
| 代理商： | CDB42528 |
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CS42526
52
DS585PP5
6.6.5
HIGH PASS FILTER FREEZE (HPF_FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig-
ital Filter Characteristics” on page 9.
6.6.6
CODEC SERIAL PORT MASTER/SLAVE SELECT (CODEC_SP M/S)
Default = 0
Function:
In Master mode, CX_SCLK and CX_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave mode, CX_SCLK and CX_LRCK become in-
puts. If the internal MCLK is sourced from the output of the PLL and the SAI serial port is in Master
Mode, then one of these conditions must be met for proper operation:
1). The codec serial port, CX_SP, must also be in Master Mode,
2). If the CX_SP is in slave mode, then CX_LRCK and CX_SCLK must be present.
6.6.7
SERIAL AUDIO INTERFACE SERIAL PORT MASTER/SLAVE SELECT (SAI_SP M/S)
Default = 0
Function:
In Master mode, SAI_SCLK and SAI_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave mode, SAI_SCLK and SAI_LRCK become
inputs. If the internal MCLK is sourced from the output of the PLL and the SAI serial port is in Master
Mode, then one of these conditions must be met for proper operation:
1). The codec serial port, CX_SP, must also be in Master Mode,
2). If the CX_SP is in slave mode, then CX_LRCK and CX_SCLK must be present.
6.7
Clock Control (address 06h)
6.7.1
RMCK DIVIDE (RMCK_DIVX)
Default = 00
Function:
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
7
6
5
4
3
2
1
0
RMCK_DIV1
RMCK_DIV0
OMCK Freq1
OMCK Freq0
PLL_LRCK
SW_CTRL1
SW_CTRL0
FRC_PLL_LK
RMCK_DIV1 RMCK_DIV0
0
0
1
1
Description
Divide by 1
Divide by 2
Divide by 4
Multiply by 2
0
1
0
1
Table 10. RMCK Divider Settings
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