參數(shù)資料
型號: CDB42528
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
中文描述: 114分貝192千赫6通道編解碼器與S / PDIF接收器
文件頁數(shù): 79/90頁
文件大?。?/td> 1560K
代理商: CDB42528
DS585PP5
79
CS42526
12.APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor-
mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the
S/PDIF preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component chang-
es. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an
S/PDIF data stream.
Phase
Comparator
and Charge Pump
÷
N
VCO
RMCK
INPUT
CRIP
CFILT
RFILT
Figure 27. PLL Block Diagram
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PDF描述
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
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