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參數(shù)資料
| 型號： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 5/50頁 |
| 文件大?。?/td> | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
272432–3
(A) Crystal Connection
NOTE:
The L
1
C
1
network is
only
required when using a third-overtone crystal.
272432–4
(B) Clock Connection
Figure 2. Clock Configurations
80C186EA PERIPHERAL
ARCHITECTURE
The 80C186EA has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact, yet powerful system. The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e.g., the
interrupt control unit supports interrupt requests
from the timer/counters or DMA channels).
The list of integrated peripherals include:
#
4-Input Interrupt Control Unit
#
3-Channel Timer/Counter Unit
#
2-Channel DMA Unit
#
13-Output Chip-Select Unit
#
Refresh Control Unit
#
Power Management logic
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB). The PCB
can be located in either memory or I/O space on
any 256 byte address boundary.
Figure 3 provides a list of the registers associated
with the PCB when the processor’s Interrupt Control
Unit is in Master Mode. In Slave Mode, the defini-
tions of some registers change. Figure 4 provides
register definitions specific to Slave Mode.
Interrupt Control Unit
The 80C186EA can receive interrupts from a num-
ber of sources, both internal and external. The Inter-
rupt Control Unit (ICU) serves to merge these re-
quests on a priority basis, for individual service by
the CPU. Each interrupt source can be independent-
ly masked by the Interrupt Control Unit or all inter-
rupts can be globally masked by the CPU.
Internal interrupt sources include the Timers and
DMA channels. External interrupt sources come
from the four input pins INT3:0. The NMI interrupt
pin is not controlled by the ICU and is passed direct-
ly to the CPU. Although the timers only have one
request input to the ICU, separate vector types are
generated to service individual interrupts within the
Timer Unit.
Timer/Counter Unit
The 80C186EA Timer/Counter Unit (TCU) provides
three 16-bit programmable timers. Two of these are
highly flexible and are connected to external pins for
control or clocking. A third timer is not connected to
any external pins and can only be clocked internally.
However, it can be used to clock the other two timer
channels. The TCU can be used to count external
events, time external events, generate non-repeti-
tive waveforms, generate timed interrupts, etc.
5
5
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