參數(shù)資料
型號: C186EA20
廠商: Intel Corp.
元件分類: DC/DC變換器
英文描述: RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述: 16位高集成嵌入式處理器
文件頁數(shù): 14/50頁
文件大?。?/td> 709K
代理商: C186EA20
80C186EA/80C188EA, 80L186EA/80L188EA
Table 3. Pin Descriptions
(Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
Description
MCS0/PEREQ
MCS1/ERROR
MCS2
MCS3/NCS
I/O
A(L)
H(1)
R(1)
P(1)
These pins provide a multiplexed function. If enabled,
these pins normally comprise a block of
Mid-Range Chip
Select
outputs which will go active whenever the address
of a memory bus cycle is within the address limitations
programmed by the user. In Numerics Mode (80C186EA
only), three of the pins become handshaking pins for the
80C187. The
CoProcessor REQuest
input signals that a
data transfer is pending.
ERROR
is an input which
indicates that the previous numerics coprocessor
operation resulted in an exception condition. An interrupt
Type 16 is generated when ERROR is sampled active at
the beginning of a numerics operation.
Numerics
Coprocessor Select
is an output signal generated when
the processor accesses the 80C187.
PCS4:0
O
H(1)
R(1)
P(1)
Peripheral Chip Selects
go active whenever the address
of a memory or I/O bus cycle is within the address
limitations programmed by the user.
PCS5/A1
PCS6/A2
O
H(1)/H(X)
R(1)
P(1)
These pins provide a multiplexed function. As additional
Peripheral Chip Selects,
they go active whenever the
address of a memory or I/O bus cycle is within the
address limitations by the user. They may also be
programmed to provide latched
Address
A2:1 signals.
T0OUT
T1OUT
O
H(Q)
R(1)
P(Q)
Timer OUTput
pins can be programmed to provide a
single clock or continuous waveform generation,
depending on the timer mode selected.
T0IN
T1IN
I
A(L)
A(E)
Timer INput
is used either as clock or control signals,
depending on the timer mode selected.
DRQ0
DRQ1
I
A(L)
DMA ReQuest
is asserted by an external request when it
is prepared for a DMA transfer.
INT0
INT1/SELECT
I
A(E,L)
Maskable
INTerrupt
input will cause a vector to a specific
Type interrupt routine. To allow interrupt expansion, INT0
and/or INT1 can be used with INTA0 and INTA1 to
interface with an external slave controller. INT1 becomes
SELECT when the ICU is configured for Slave Mode.
INT2/INTA0
INT3/INTA1/IRQ
I/O
A(E,L)
H(1)
R(Z)
P(1)
These pins provide multiplexed functions. As inputs, they
provide a maskable
INTerrupt
that will cause the CPU to
vector to a specific Type interrupt routine. As outputs,
each is programmatically controlled to provide an
INTerrupt Acknowledge
handshake signal to allow
interrupt expansion. INT3/INTA1 becomes
IRQ
when the
ICU is configured for Slave Mode.
N.C.
No Connect.
For compatibility with future products, do not
connect to these pins.
NOTE:
Pin names in parentheses apply to the 80C188EA and 80L188EA.
14
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