參數(shù)資料
型號： C186EA20
廠商： Intel Corp.
元件分類： DC/DC變換器
英文描述： RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述： 16位高集成嵌入式處理器
文件頁數(shù)： 45/50頁
文件大小： 709K
代理商： C186EA20
80C186EA/80C188EA, 80L186EA/80L188EA
INSTRUCTION SET SUMMARY
(Continued)
Function
Format
80C186EA
Clock
Cycles
80C188EA
Clock
Cycles
Comments
DATA TRANSFER
(Continued)
SEGMENT
e
Segment Override:
CS
0 0 1 0 1 1 1 0
2
2
SS
0 0 1 1 0 1 1 0
2
2
DS
0 0 1 1 1 1 1 0
2
2
ES
0 0 1 0 0 1 1 0
2
2
ARITHMETIC
ADD
e
Add:
Reg/memory with register to either
0 0 0 0 0 0 d w
mod reg r/m
3/10
3/10
*
Immediate to register/memory
1 0 0 0 0 0 s w
mod 0 0 0 r/m
data
data if s w
e
01
4/16
4/16
*
Immediate to accumulator
0 0 0 0 0 1 0 w
data
data if w
e
1
3/4
3/4
8/16-bit
ADC
e
Add with carry:
Reg/memory with register to either
0 0 0 1 0 0 d w
mod reg r/m
3/10
3/10
*
Immediate to register/memory
1 0 0 0 0 0 s w
mod 0 1 0 r/m
data
data if s w
e
01
4/16
4/16
*
Immediate to accumulator
0 0 0 1 0 1 0 w
data
data if w
e
1
3/4
3/4
8/16-bit
INC
e
Increment:
Register/memory
1 1 1 1 1 1 1 w
mod 0 0 0 r/m
3/15
3/15
*
Register
0 1 0 0 0 reg
3
3
SUB
e
Subtract:
Reg/memory and register to either
0 0 1 0 1 0 d w
mod reg r/m
3/10
3/10
*
Immediate from register/memory
1 0 0 0 0 0 s w
mod 1 0 1 r/m
data
data if s w
e
01
4/16
4/16
*
Immediate from accumulator
0 0 1 0 1 1 0 w
data
data if w
e
1
3/4
3/4
8/16-bit
SBB
e
Subtract with borrow:
Reg/memory and register to either
0 0 0 1 1 0 d w
mod reg r/m
3/10
3/10
*
Immediate from register/memory
1 0 0 0 0 0 s w
mod 0 1 1 r/m
data
data if s w
e
01
4/16
4/16
*
Immediate from accumulator
0 0 0 1 1 1 0 w
data
data if w
e
1
3/4
3/4
*
8/16-bit
DEC
e
Decrement
Register/memory
1 1 1 1 1 1 1 w
mod 0 0 1 r/m
3/15
3/15
*
Register
0 1 0 0 1 reg
3
3
CMP
e
Compare:
Register/memory with register
0 0 1 1 1 0 1 w
mod reg r/m
3/10
3/10
*
Register with register/memory
0 0 1 1 1 0 0 w
mod reg r/m
3/10
3/10
*
Immediate with register/memory
1 0 0 0 0 0 s w
mod 1 1 1 r/m
data
data if s w
e
01
3/10
3/10
*
Immediate with accumulator
0 0 1 1 1 1 0 w
data
data if w
e
1
3/4
3/4
8/16-bit
NEG
e
Change sign register/memory
1 1 1 1 0 1 1 w
mod 0 1 1 r/m
3/10
*
3/10
*
AAA
e
ASCII adjust for add
0 0 1 1 0 1 1 1
8
8
DAA
e
Decimal adjust for add
0 0 1 0 0 1 1 1
4
4
AAS
e
ASCII adjust for subtract
0 0 1 1 1 1 1 1
7
7
DAS
e
Decimal adjust for subtract
0 0 1 0 1 1 1 1
4
4
MUL
e
Multiply (unsigned):
1 1 1 1 0 1 1 w
mod 100 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
26–28
35–37
32–34
41–43
26–28
35–37
32–34
41–48
*
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*
Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
45
45
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