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參數(shù)資料
| 型號(hào)： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁(yè)數(shù)： | 10/50頁(yè) |
| 文件大小： | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
Table 2. Pin Description Nomenclature
Symbol
Description
P
G
I
O
I/O
Power Pin (Apply
a
V
CC
Voltage)
Ground (Connect to V
SS
)
Input Only Pin
Output Only Pin
Input/Output Pin
S(E)
S(L)
A(E)
A(L)
Synchronous, Edge Sensitive
Synchronous, Level Sensitive
Asynchronous, Edge Sensitive
Asynchronous, Level Sensitive
H(1)
H(0)
H(Z)
H(Q)
H(X)
Output Driven to V
CC
during Bus Hold
Output Driven to V
SS
during Bus Hold
Output Floats during Bus Hold
Output Remains Active during Bus Hold
Output Retains Current State during Bus Hold
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
Output Weakly Held at V
CC
during Reset
Output Driven to V
CC
during Reset
Output Driven to V
SS
during Reset
Output Floats during Reset
Output Remains Active during Reset
Output Retains Current State during Reset
I(1)
I(0)
I(Z)
I(Q)
I(X)
Output Driven to V
CC
during Idle Mode
Output Driven to V
SS
during Idle Mode
Output Floats during Idle Mode
Output Remains Active during Idle Mode
Output Retains Current State during Idle Mode
P(1)
P(0)
P(Z)
P(Q)
P(X)
Output Driven to V
CC
during Powerdown Mode
Output Driven to V
SS
during Powerdown Mode
Output Floats during Powerdown Mode
Output Remains Active during Powerdown Mode
Output Retains Current State during Powerdown Mode
10
10
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