參數(shù)資料
型號(hào)： C186EA20
廠商： Intel Corp.
元件分類： DC/DC變換器
英文描述： RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述： 16位高集成嵌入式處理器
文件頁數(shù)： 49/50頁
文件大?。?/td> 709K
代理商： C186EA20
80C186EA/80C188EA, 80L186EA/80L188EA
INSTRUCTION SET SUMMARY
(Continued)
Function
Format
80C186EA
Clock
Cycles
80C188EA
Clock
Cycles
Comments
PROCESSOR CONTROL
CLC
e
Clear carry
1 1 1 1 1 0 0 0
2
2
CMC
e
Complement carry
1 1 1 1 0 1 0 1
2
2
STC
e
Set carry
1 1 1 1 1 0 0 1
2
2
CLD
e
Clear direction
1 1 1 1 1 1 0 0
2
2
STD
e
Set direction
1 1 1 1 1 1 0 1
2
2
CLI
e
Clear interrupt
1 1 1 1 1 0 1 0
2
2
STI
e
Set interrupt
1 1 1 1 1 0 1 1
2
2
HLT
e
Halt
1 1 1 1 0 1 0 0
2
2
WAIT
e
Wait
1 0 0 1 1 0 1 1
6
6
if TEST
e
0
LOCK
e
Bus lock prefix
1 1 1 1 0 0 0 0
2
2
NOP
e
No Operation
1 0 0 1 0 0 0 0
3
3
(TTT LLL are opcode to processor extension)
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*
Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:
if mod
e
11 then r/m is treated as a REG field
if mod
e
00 then DISP
e
0
*
, disp-low and disp-
high are absent
if mod
e
01 then DISP
e
disp-low sign-ex-
tended to 16-bits, disp-high is absent
if mod
e
10 then DISP
e
disp-high: disp-low
if r/m
e
000 then EA
e
(BX)
a
(SI)
a
DISP
if r/m
e
001 then EA
e
(BX)
a
(DI)
a
DISP
if r/m
e
010 then EA
e
(BP)
a
(SI)
a
DISP
if r/m
e
011 then EA
e
(BP)
a
(DI)
a
DISP
if r/m
e
100 then EA
e
(SI)
a
DISP
if r/m
e
101 then EA
e
(DI)
a
DISP
if r/m
e
110 then EA
e
(BP)
a
DISP
*
if r/m
e
111 then EA
e
(BX)
a
DISP
DISP follows 2nd byte of instruction (before data if
required)
*
except if mod
e
00 and r/m
e
110 then EA
e
disp-high: disp-low.
EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenev-
er appropriate.
Segment Override Prefix
0
0
1
reg
1
1
0
reg is assigned according to the following:
Segment
Register
ES
CS
SS
DS
reg
00
01
10
11
REG is assigned according to the following table:
16-Bit (w
e
1)
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
111 DI
8-Bit (w
e
0)
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register. The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.
49
49
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