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參數(shù)資料
| 型號： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 28/50頁 |
| 文件大?。?/td> | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
AC SPECIFICATIONS
AC CharacteristicsD80L186EA13/80L186EA8
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
SYNCHRONOUS INPUTS
13 MHz
8 MHz
T
CHIS
T
CHIH
T
CLIS
T
CLIH
T
CLIS
T
CLIH
T
CLIS
T
CLIH
TEST, NMI, INT3:0, T1:0IN, ARDY
22
22
ns
1, 9
TEST, NMI, INT3:0, T1:0IN, ARDY
3
3
ns
1, 9
AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0
22
22
ns
1, 10
AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0
3
3
ns
1, 10
HOLD
22
22
ns
1, 9
HOLD
3
3
ns
1, 9
RESIN (to CLKIN)
22
22
ns
1, 9
RESIN (from CLKIN)
3
3
ns
1, 9
NOTES:
1. See
AC Timing Waveforms
, for waveforms and definition.
2. Measured at V
IH
for high time, V
IL
for low time.
3. Only required to guarantee I
CC
. Maximum limits are bounded by T
C
, T
CH
and T
CL
.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. T
CHOV1
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. T
CHOV2
applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
11. T
CHOVS
applies to BHE (RFSH) and A19:16 only after a HOLD release.
12. Pin names in parentheses apply to the 80C188EA/80L188EA.
28
28
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