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參數(shù)資料
| 型號： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 27/50頁 |
| 文件大?。?/td> | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
AC SPECIFICATIONS
AC CharacteristicsD80L186EA13/80L186EA8
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
INPUT CLOCK
13 MHz
8 MHz
T
F
T
C
T
CH
T
CL
T
CR
T
CF
OUTPUT CLOCK
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
0
26
%
%
%
8
8
0
16
%
%
%
8
8
MHz
ns
ns
ns
ns
ns
1
1
38.5
12
12
1
1
62.5
12
12
1
1
1, 2
1, 2
1, 3
1, 3
T
CD
T
T
PH
T
PL
T
PR
T
PF
OUTPUT DELAYS
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
0
45
0
95
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
2
*
T
C
2
*
T
C
(T/2)
b
5
(T/2)
b
5
1
1
(T/2)
b
5
(T/2)
b
5
1
1
12
12
12
12
T
CHOV1
T
CHOV2
ALE, LOCK
3
27
3
27
ns
1, 4, 6, 7
MCS3:0, LCS, UCS,
PCS6:0, RD, WR
3
32
3
32
ns
1, 4,
6, 8
T
CHOV3
S2:0 (DEN), DT/R,
BHE (RFSH), A19:16
3
30
3
30
ns
1
T
CLOV1
LOCK, RESOUT, HLDA,
T0OUT, T1OUT
3
27
3
27
ns
1, 4, 6
T
CLOV2
RD, WR, MCS3:0, LCS,
UCS, PCS6:0, INTA1:0
3
32
3
35
ns
1, 4, 6
T
CLOV3
T
CLOV4
T
CLOV5
T
CHOF
BHE (RFSH), DEN, A19:16
3
30
3
30
ns
1, 4, 6
AD15:0 (A15:8, AD7:0)
3
34
3
35
ns
1, 4, 6
S2:0
3
38
3
40
ns
1, 4, 6
RD, WR, BHE (RFSH),
DT/R, LOCK,
S2:0, A19:16
0
27
0
27
ns
1
T
CLOF
DEN, AD15:0
(A15:8, AD7:0)
0
27
0
27
ns
1
NOTES:
1. See
AC Timing Waveforms
, for waveforms and definition.
2. Measured at V
IH
for high time, V
IL
for low time.
3. Only required to guarantee I
CC
. Maximum limits are bounded by T
C
, T
CH
and T
CL
.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. T
CHOV1
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. T
CHOV2
applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
11. T
CHOVS
applies to BHE (RFSH) and A19:16 only after a HOLD release.
12. Pin names in parentheses apply to the 80C188EA/80L188EA.
27
27
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