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參數(shù)資料
| 型號(hào)： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類(lèi)： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁(yè)數(shù)： | 36/50頁(yè) |
| 文件大?。?/td> | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
BUS CYCLE WAVEFORMS
Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in
the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information
present in
AC Specifications
allow the user to determine all the critical timing analysis needed for a given
application.
272432-17
NOTES:
1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.
2. Pin names in parentheses apply to the 80C188EA.
Figure 17. Read, Fetch and Refresh Cycle Waveform
36
36
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