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參數(shù)資料
| 型號： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 29/50頁 |
| 文件大?。?/td> | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
AC SPECIFICATIONS
(Continued)
Relative Timings (80C186EA25/20/13, 80L186EA13/8)
Symbol
Parameter
Min
Max
Unit
Notes
RELATIVE TIMINGS
T
LHLL
ALE Rising to ALE Falling
T
b
15
ns
T
AVLL
Address Valid to ALE Falling
(/2
T
b
10
ns
T
PLLL
Chip Selects Valid to ALE Falling
(/2
T
b
10
ns
1
T
LLAX
Address Hold from ALE Falling
(/2
T
b
10
ns
T
LLWL
ALE Falling to WR Falling
(/2
T
b
15
ns
1
T
LLRL
ALE Falling to RD Falling
(/2
T
b
15
ns
1
T
RHLH
RD Rising to ALE Rising
(/2
T
b
10
ns
1
T
WHLH
WR Rising to ALE Rising
(/2
T
b
10
ns
1
T
AFRL
Address Float to RD Falling
0
ns
T
RLRH
RD Falling to RD Rising
(2
*
T)
b
5
(2
*
T)
b
5
ns
2
T
WLWH
WR Falling to WR Rising
ns
2
T
RHAV
RD Rising to Address Active
T
b
15
ns
T
WHDX
Output Data Hold after WR Rising
T
b
15
ns
T
WHDEX
WR Rising to DEN Rising
(/2
T
b
10
ns
1
T
WHPH
WR Rising to Chip Select Rising
(/2
T
b
10
ns
1, 4
T
RHPH
RD Rising to Chip Select Rising
(/2
T
b
10
ns
1, 4
T
PHPL
CS Inactive to CS Active
(/2
T
b
10
ns
1
T
DXDL
DEN Inactive to DT/R Low
0
ns
5
T
OVRH
ONCE (UCS, LCS) Active to RESIN Rising
T
ns
3
T
RHOX
ONCE (UCS, LCS) to RESIN Rising
T
ns
3
NOTES:
1. Assumes equal loading on both pins.
2. Can be extended using wait states.
3. Not tested.
4. Not applicable to latched A2:1. These signals change only on falling T
1
.
5. For write cycle followed by read cycle.
6. Operating conditions for 25 MHz are 0
§
C to
a
70
§
C, V
CC
e
5.0V
g
10%.
29
29
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