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參數(shù)資料
| 型號： | C186EA20 |
| 廠商： | Intel Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 13/50頁 |
| 文件大小： | 709K |
| 代理商： | C186EA20 |
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80C186EA/80C188EA, 80L186EA/80L188EA
Table 3. Pin Descriptions
(Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
Description
WR/QS1
O
H(Z)
R(Z)
P(1)
WRite
output signals that data available on the data bus are to be
written into the accessed memory or I/O device. In Queue Status
Mode, QS1 provides queue status information along with QS0.
ARDY
I
A(L)
S(L)
Asychronous ReaDY
is an input to signal for the end of a bus cycle.
ARDY is asynchronous on rising CLKOUT and synchronous on falling
CLKOUT. ARDY or SRDY must be active to terminate any processor
bus cycle, unless they are ignored due to correct programming of the
Chip Select Unit.
SRDY
I
S(L)
Synchronous ReaDY
is an input to signal for the end of a bus cycle.
ARDY or SRDY must be active to terminate any processor bus cycle,
unless they are ignored due to correct programming of the Chip Select
Unit.
DEN
O
H(Z)
R(Z)
P(1)
Data ENable
output to control the enable of bidirectional transceivers
when buffering a system. DEN is active only when data is to be
transferred on the bus.
DT/R
O
H(Z)
R(Z)
P(X)
Data Transmit/Receive
output controls the direction of a bi-
directional buffer in a buffered system. DT/R is only available on the
QFP (EIAJ) package and the SQFP package.
LOCK
O
H(Z)
R(WH)
P(1)
LOCK
output indicates that the bus cycle in progress is not to be
interrupted. The processor will not service other bus requests (such
as HOLD) while LOCK is active. This pin is configured as a weakly
held high input while RESIN is active and must not be driven low.
HOLD
I
A(L)
HOLD
request input to signal that an external bus master wishes to
gain control of the local bus. The processor will relinquish control of
the local bus between instruction boundaries not conditioned by a
LOCK prefix.
HLDA
O
H(1)
R(0)
P(0)
HoLD Acknowledge
output to indicate that the processor has
relinquished control of the local bus. When HLDA is asserted, the
processor will (or has) floated its data bus and control signals allowing
another bus master to drive the signals directly.
UCS
O
H(1)
R(1)
P(1)
Upper Chip Select
will go active whenever the address of a memory
or I/O bus cycle is within the address limitations programmed by the
user. After reset, UCS is configured to be active for memory accesses
between 0FFC00H and 0FFFFFH. During a processor reset, UCS and
LCS are used to enable ONCE Mode.
LCS
O
H(1)
R(1)
P(1)
Lower Chip Select
will go active whenever the address of a memory
bus cycle is within the address limitations programmed by the user.
LCS is inactive after a reset. During a processor reset, UCS and LCS
are used to enable ONCE Mode.
NOTE:
Pin names in parentheses apply to the 80C188EA and 80L188EA.
13
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