1H1 RISING EDGE. " />
參數(shù)資料
型號: AD9974BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 8/52頁
文件大?。?/td> 0K
描述: IC CCDSP DUAL 14BIT 100-CSPBGA
標準包裝: 1
類型: CCD 信號處理器,14 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 55mA
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(9x9)
包裝: 標準包裝
其它名稱: AD9974BBCZRLDKR
AD9974
Rev. A | Page 16 of 52
12
43
H1 TO H4 PROGRAMMABLE LOCATIONS:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H2 RISING EDGE.
4H2 FALLING EDGE.
H2, H4
H1, H3
0
59
55
-0
19
Figure 19. HCLK Mode 2 Operation
12
4
3
H1 TO H4 PROGRAMMABLE LOCATIONS:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H3 RISING EDGE.
4H3 FALLING EDGE.
H3
H1
H2
H4
05
95
5-
0
20
Figure 20. HCLK Mode 3 Operation
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
P[0]
CLI
RG
P[64] = P[0]
CCD
SIGNAL
P[32]
P[16]
P[48]
POSITION
H2
RGr[0]
RGf[16]
SHD
SHDLOC[0]
H1
H1r[0]
H1f[32]
tS1
SHP
SHPLOC[32]
DOUTPHASEP
DATAPHASEP[32]
tDOUTINH
tSHDINH
tSHPINH
05
95
5-
0
21
Figure 21. High Speed Timing Default Locations
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