參數(shù)資料
型號： AD9974BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 15/52頁
文件大?。?/td> 0K
描述： IC CCDSP DUAL 14BIT 100-CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 55mA
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD9974BBCZRLDKR
AD9974
Rev. A | Page 22 of 52
HBLK Mode 1 Operation
Enable multiple repeats of the HBLK signal by setting
HBLK_MODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 28).
Separate toggle positions are available for even and odd lines.
If alternation is not needed, load the same values into the registers
for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. Separate toggle positions are available for even and odd
lines. If even/odd line alternation is not required, load the same
values into the registers for even (HBLKTOGE) and odd
(HBLKTOGO) lines.
Increasing H-Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse
width to be increased during the HBLK interval. As shown in
Figure 29, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable this
feature, the HCLK_WIDTH register (Address 0x34[7:4]) is set to
a value between 1 and 15. When this register is set to 0, the wide
HCLK feature is disabled. The reduced frequency occurs only for
H1 to H4 pulses that are located within the HBLK area.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK Mode 0
and HBLK Mode 1, not in HBLK Mode 2.
Table 13. HCLK Width Register
Register
Length (Bits)
Description
HCLK_WIDTH
4
Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0 = same frequency as pixel rate.
1 = 1/2 pixel frequency, that is, doubles the HCLK pulse width.
2 = 1/4 pixel frequency.
3 = 1/6 pixel frequency.
4 = 1/8 pixel frequency.
5 = 1/10 pixel frequency.
…
15 = 1/30 pixel frequency.
HBLK
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS.
H1/H3
H2/H4
HBLKSTART HBLKTOGE1
HBLKTOGE2
HBLKEND
HBLKTOGE3
HBLKTOGE4
HBLKLEN
HBLKREP NUMBER 1
HBLKREP NUMBER 2
HBLKREP NUMBER 3
HBLKREP = 3
05
95
5-
02
8
Figure 28. HBLK Repeating Pattern Using HBLKMODE = 1
HBLK
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER.
H1/H3
H2/H4
1/FPIX
2 × (1/FPIX)
0
59
55
-02
9
Figure 29. Generating Wide H-Clock Pulses During HBLK Interval
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