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參數(shù)資料
| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應商設備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 9 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
A1 CORNER
INDEX AREA
23
45678
9 10
A
B
C
D
E
F
G
H
J
K
AD9974
TOP VIEW
(Not to Scale)
05
95
5-
0
03
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Ball Location
Mnemonic
Type1
Description
B2
SL_A
DI
3-Wire Serial Load for Channel A.
C2
SDATA_A
DI
3-Wire Serial Data for Channel A.
D2
SCK_A
DI
3-Wire Serial Clock for Channel A.
C1
REFT_A
AO
Reference with Top Decoupling for Channel A. Decouple with 0.1 μF to AVSS_A.
D1
REFB_A
AO
Reference with Bottom Decoupling for Channel A. Decouple with 0.1 μF to AVSS_A.
A1
CCDINM_A
AI
Analog Input for Channel A Image Sensor Signal.
F4
H1_A
DO
CCD Horizontal Clock 1 for Channel A.
F3
H2_A
DO
CCD Horizontal Clock 2 for Channel A.
D4
H3_A
DO
CCD Horizontal Clock 3 for Channel A.
D3
H4_A
DO
CCD Horizontal Clock 4 for Channel A.
B4
RG_A
DO
CCD Reset Gate Clock for Channel A.
J2
DRVSS_A
P
Digital Driver Ground for Channel A.
K3
DRVDD_A
P
Digital Driver Supply for Channel A: 1.8 V or 3.0 V.
E3
HVSS_A
P
H1_A to H4_A Driver Ground for Channel A.
E4
HVDD_A
P
H1_A to H4_A Driver Supply for Channel A: 3.0 V.
C3
RGVSS_A
P
RG_A Driver Ground for Channel A.
C4
RGVDD_A
P
RG_A Driver Supply for Channel A: 3.0 V.
B3
IOVDD_A
P
Digital I/O Supply: 1.8 V or 3.0 V (HD, VD, SL, SCK, SDATA) and LDO Input (3.0 V Only)
When LDO Is Used.
A4
CLI_A
DI
Master Clock Input for Channel A.
B1
AVSS_A
P
Analog Ground for Channel A.
A2
CCDINP_A
AI
Analog Input for Channel A Image Sensor Signal.
F2
DVSS_A
P
Digital Ground for Channel A.
F1
DVDD_A
P
Digital Supply for Channel A: 1.8 V.
E2
VD_A
DI
Vertical Sync Pulse for Channel A.
E1
HD_A
DI
Horizontal Sync Pulse for Channel A.
B8
SL_B
DI
3-Wire Serial Load for Channel B.
C8
SDATA_B
DI
3-Wire Serial Data for Channel B.
A5
LDO_OUT_A
P
1.8 V LDO Output from Channel A.
A6
CCDINM_B
AI
Analog Input for Channel B Image Sensor Signal.
D8
SCK_B
DI
3-Wire Serial Clock for Channel B.
C7
REFT_B
AO
Reference with Top Decoupling for Channel B. Decouple with 0.1 μF to AVSS_B.
D7
REFB_B
AO
Reference with Bottom Decoupling for Channel B. Decouple with 0.1 μF to AVSS_B.
A7
CCDINP_B
AI
Analog Input for Channel B Image Sensor Signal.
F10
H1_B
DO
CCD Horizontal Clock 1 for Channel B.
F9
H2_B
DO
CCD Horizontal Clock 2 for Channel B.
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