參數(shù)資料
型號(hào)： AD9974BBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 0K
描述： IC CCDSP DUAL 14BIT 100-CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 55mA
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD9974BBCZRLDKR
AD9974
Rev. A | Page 24 of 52
HBLK, PBLK, and CLPOB Toggle Positions
The AD9974 uses an internal horizontal pixel counter to position
the HBLK, PBLK, and CLPOB toggle positions. The horizontal
counter does not reset to 0 until 12 CLI periods after the falling
edge of HD. This 12-cycle pipeline delay must be considered
when determining the register toggle positions. For example, if
CLPOB_TOG1 is 100 and the pipeline delay is not considered,
the final toggle position is applied at 112. To obtain the correct
toggle positions, the toggle position registers must be set to the
desired toggle position minus 12.
For example, if the desired toggle position is 100, CLPOB_TOG
should be set to 88 (that is, 100 12). Figure 49 shows the 12-cycle
pipeline delay referenced to the falling edge of HD.
Caution
Toggle positions cannot be programmed during the 12-cycle
delay from the HD falling edge until the H-counter has reset.
See Figure 33 for an example of this restriction.
1. HBLKTOG1
60
(60 – 12) = 48
2. HBLKTOG2
100
(100 – 12) = 88
3. CLPOB_TOG1
103
(103 – 12) = 91
4. CLPOB_TOG2
112
(112 – 12) = 100
DESIRED
TOGGLE
POSITION
ACTUAL
REGISTER
VALUE
H1
CLPOB
PIXEL NO.
HD
112
103
100
60
0
12
34
05
95
5-
03
2
Figure 32. Example of Register Setting to Obtain Desired Toggle Positions
VD
HD
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
H-COUNTER
(PIXEL COUNTER)
N-1
N
0
1
2
N-2
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
H-COUNTER
RESET
X
05
95
5
-03
3
Figure 33. Restriction for Toggle Position Placement
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