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參數(shù)資料
| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 37 of 52
CIRCUIT CONFIGURATION
The AD9974 recommended circuit configuration is shown in
Figure 51. Achieving good image quality from the AD9974
requires careful attention to PCB layout. All signals should
be routed to maintain low noise performance. The CCD_A
and CCD_B output signals should be directly routed to Pin A1
and Pin A7, respectively, through a 0.1 μF capacitor. The master
clock, CLI_X, should be carefully routed to Pin A3 and Pin A9
to minimize interference with the CCDIN_X, REFT_X, and
REFB_X signals.
The digital outputs and clock inputs should be connected to the
digital ASIC away from the analog and CCD clock signals. Placing
series resistors close to the digital output pins may help reduce
digital code transition noise. If the digital outputs must drive
a load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
outputs of the AD9974 can be selected to output data in gray
code format using Register 0x01[2]. Compared with binary
coding, gray coding helps reduce potential digital transition noise.
The H1_X to H4_X and RG_X traces should have low inductance
to avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand
on H1_X to H4_X from the capacitive load of the CCD. If possible,
physically locating the AD9974 closer to the CCD reduces the
inductance on these lines. As always, the routing path should be
as direct as possible from the AD9974 to the CCD.
The CLI_X and CCDIN_X PCB traces should be carefully matched
in length and impedance to achieve optimal channel-to-channel
matching performance.
3 V System Compatibility
The AD9974 typical circuit connections for a 3 V system are
shown in Figure 51. This application uses an external 3.3 V
supply connected to the IOVDD input of the AD0074, which
also serves as the LDO input. The LDO generates a 1.8 V output
for the AD9974 core supply voltages, AVDD and DVDD. The
LDOOUT pin can then be connected directly to the AVDD and
DVDD pins. In this configuration, the LDOEN pin is tied high
to enable the LDO.
Alternatively, a separate 1.8 V regulated supply voltage may be
used to power the AVDD and DVDD pins. In this case, the
LDOOUT pin needs to be left floating, and the LDOEN pin
needs to be grounded. A typical circuit configuration for a 1.8 V
system is shown in Figure 51.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 51, a single ground plane is recommended
for the AD9974. This ground plane needs to be as continuous as
possible, particularly around the P-type, AI-type, and A-type
pins to ensure that all analog decoupling capacitors provide the
lowest possible impedance path between the power and bypass
pins and their respective ground pins. All high frequency
decoupling capacitors need to be located as close as possible to
the package pins.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There also needs to be
a 4.7 μF or larger bypass capacitor for each main supply, that is,
AVDD, RGVDD, HVDD, and DRVDD, although this is not
necessary for each individual pin. In most applications, it is
easier to share the supply for RGVDD and HVDD, which can
be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply can be used for DRVDD, but
this supply pin still needs to be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
The reference bypass pins (REFT, REFB) must be decoupled to
ground as close as possible to their respective pins. The bridge
capacitor between REFT and REFB is recommended for pixel
rates greater than 40 MHz. The analog input capacitor (CCDINM,
CCDINP) also needs to be located close to the pin.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END WITH HALF DUPLEX - Tape and Reel |
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