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參數(shù)資料
| 型號(hào)： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 46 of 52
Address
Data Bit
Content
Default
Value
Update
Name
Description
[10:8]
1
H3DRV
H3 Drive Strength.
[11]
Unused
Set unused bits to 0.
[14:12]
1
H4DRV
H4 Drive Strength.
[15]
Unused
Set unused bits to 0.
[18:16]
TESTMODE
Test Operation Only. Set to 0.
[19]
Unused
Set unused bits to 0.
[22:20]
1
RGDRV
RG Drive Strength.
[27:23]
0
Unused
Set unused bits to 0.
0x36
[5:0]
0
SCK
SHDLOC
SHD Sampling Edge Location.
[11:6]
20
SHPLOC
SHP Sampling Edge Location.
[17:12]
10
SHPWIDTH
SHP Width. Controls input dc restore switch active time.
[27:18]
Unused
Set unused bits to 0.
0x37
[5:0]
0
SCK
DOUTPHASEP
DOUT Positive Edge Phase Control.
[11:6]
20
DOUTPHASEN
DOUT Negative Edge Phase Control.
Set DOUTPHASEN = DOUTPHASEP + 0x20.
[12]
0
DCLKMODE
0 = DCLK tracks DOUT phase.
1 = DCLK is CLI post-Schmitt trigger and post-divider when
CLIDIVIDE = 1.
[14:13]
2
CLKDATA_SEL
Data Output Clock Selection.
0 = no delay.
1 = ~4 ns.
2 = ~8 ns.
3 = ~12 ns.
[15]
0
INV_DCLK
0 = no invert.
1 = invert DCLK to output.
[27:16]
Unused
Set unused bits to 0.
0x38
[27:0]
Unused
Set unused register to 0 if this register is accessed.
0x39
[27:0]
Unused
Set unused register to 0 if this register is accessed.
0x3A
[27:0]
Unused
Set unused register to 0 if this register is accessed.
0x3B
[27:0]
Unused
Set unused register to 0 if this register is accessed.
0x3C
[27:0]
Unused
Set unused register to 0 if this register is accessed.
[27:0]
Unused
Set unused register to 0 if this register is accessed.
Table 28. Test Registers—Do Not Access
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x3E
[18:0]
4B020
SCK
TESTMODE
Test Operation Only. Set to 4B020.
[27:19]
Unused
Set unused bits to 0.
0x3F
[27:0]
SCK
Unused
Set unused register to 0 if these registers are accessed.
0x40
[3:0]
F
SCK
TESTMODE
Test Operation Only. Set to F if accessed.
[9:4]
0
TESTMODE
Test Operation Only. Set to 0.
[27:10]
Unused
Set unused bits to 0.
0x41 to
0x4F
[27:0]
SCK
Unused
Set unused register to 0 if these registers are accessed.
0x50 to
0x5F
[27:0]
SCK
Unused
Set unused register to 0 if these registers are accessed.
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