參數(shù)資料
型號： AD9974BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 44/52頁
文件大?。?/td> 0K
描述： IC CCDSP DUAL 14BIT 100-CSPBGA
標準包裝： 1
類型： CCD 信號處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 55mA
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 標準包裝
其它名稱： AD9974BBCZRLDKR
AD9974
Rev. A | Page 49 of 52
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x02
[12:0]
X
VD
SCP4
Sequence Change Position 4.
[25:13]
X
SCP5
Sequence Change Position 5.
[27:26]
X
Unused
Set unused bits to 0.
0x03
[12:0]
X
VD
SCP6
Sequence Change Position 6.
[25:13]
X
SCP7
Sequence Change Position 7.
[27:26]
X
Unused
Set unused bits to 0.
0x04
[12:0]
X
VD
SCP8
Sequence Change Position 8.
[27:13]
Unused
Set unused bits to 0.
0x05
[4:0]
X
VD
HPAT_SEL0
Selected H-Pattern for First Region in Field.
[9:5]
X
HPAT_SEL1
Selected H-Pattern for Second Region in Field.
[14:10]
X
HPAT_SEL2
Selected H-Pattern for Third Region in Field.
[19:15]
X
HPAT_SEL3
Selected H-Pattern for Fourth Region in Field.
[24:20]
X
HPAT_SEL4
Selected H-pattern for fifth region in field.
[27:25]
X
Unused
Set unused bits to 0.
0x06
[4:0]
X
VD
HPAT_SEL5
Selected H-Pattern for Sixth Region in Field.
[9:5]
X
HPAT_SEL6
Selected H-Pattern for Seventh Region in Field.
[14:10]
X
HPAT_SEL7
Selected H-Pattern for Eighth Region in Field.
[19:15]
X
HPAT_SEL8
Selected H-Pattern for Ninth Region in Field.
[27:20]
X
Unused
Set unused bits to 0.
0x07
[27:0]
X
VD
Unused
Set unused bits to 0.
0x08
[8:0]
X
VD
CLPOB_POL
CLPOB Start Polarity Settings.
[17:9]
X
CLPOB_PAT
CLPOB Pattern Selector.
0 = CLPOB0_TOG registers are used.
1 = CLPOB1_TOG registers are used.
[27:18]
X
Unused
Set unused bits to 0.
0x09
[12:0]
X
VD
CLPOBMASKSTART1
CLPOB Mask 1 Start Position.
[25:13]
X
CLOBMASKEND1
CLPOB Mask 1 End Position.
[27:26]
Unused
Set unused bits to 0.
0xA
[12:0]
X
VD
CLPOBMASKSTART2
CLPOB Mask 2 Start Position.
[25:13]
X
CLOBMASKEND2
CLPOB Mask 2 End Position.
[27:26]
X
Unused
Set unused bits to 0.
0xB
[12:0]
X
VD
CLPOBMASKSTART3
CLPOB Mask 3 Start Position.
[25:13]
X
CLOBMASKEND3
CLPOB Mask 3 End Position.
[27:26]
X
Unused
Set unused bits to 0.
0xC
[8:0]
X
VD
PBLK_POL
PBLK Start Polarity Settings for Sequence 0 to Sequence 8.
[17:9]
X
PBLK_PAT
PBLK Pattern Selector.
0 = PBLK0_TOG registers are used.
1 = PBLK1_TOG registers are used.
[27:18]
X
Unused
Set unused bits to 0
0xD
[12:0]
X
VD
PBLKMASKSTART1
PBLK Mask Region 1 Start Position.
[25:13]
X
PBLKMASKEND1
PBLK Mask Region 1 End Position.
[27:26]
X
Unused
Set unused bits to 0.
0xE
[12:0]
X
VD
PBLKMASKSTART2
PBLK Mask Region 2 Start Position.
[25:13]
X
PBLKMASKEND2
PBLK Mask Region 2 End Position.
[27:26]
X
Unused
Set unused bits to 0.
0xF
[12:0]
X
VD
PBLKMASKSTART3
PBLK Mask Region 3 Start Position.
[25:13]
X
PBLKMASKEND3
PBLK Mask Region 3 End Position.
[27:26]
X
Unused
Set unused bits to 0.
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