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參數(shù)資料
| 型號： | XRT83L34IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128 |
| 文件頁數(shù)： | 81/82頁 |
| 文件大?。?/td> | 447K |
| 代理商： | XRT83L34IV |
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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
78
REVISIONS
R
EVISION
D
ESCRIPTION
A1.0.1
thru
A1.0.7
Advanced Versions
P1.1.0
Preliminary release version
P1.2.0
Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Micropro-
cessor description table by register number. Moved absolute maximum and Dc electrical characteristics
before AC electrical characteristics. Replaced TBD’s in electrical ables. Reformated table of contents.
P1.2.1
Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register binary bits.
P1.2.2
Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the FIFO size
is selected by the jitter attenuator select.
P1.2.3
Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path and
FIFO size.
P1.2.4
Corrected typos in figures 6 and 8. Added Jitter attenuator tables in microprocessor register tables. Mod-
ified microprocessor descrptions, timing diagrams and electrical characteristics.
P1.2.5
Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT, replace IMASK
bit to a “1” with GIE bit to a “0”.
P1.2.6
New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers.
P1.2.7
Revised Microprocessor interface timing diagrams and data.
P1.2.8
Corrected microprocessor timing information and edited Redundancy section.
P1.2.9
Edited section on RLOS for more detailed explanation.
P1.3.0
Changed definition of TXON_n pin. RXON_n bit included in register tables. Rx transformer ratio changed
from 2:1 to 1:1. Description of Arbitrary Pulse and Gap Clock support added.
P1.3.1
Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected
table 37.
P1.3.2
Swapped the function of μPTS1 and μPTS2. Replaced μProcessor timing diagrams and timing informa-
tion, (Figures 29 and 30 -- Tables 49 and 50).
P1.3.3
Updated the Power Consumption numbers.
P1.3.4
Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34IV-F | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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