參數(shù)資料
型號: XRT83L34IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù): 56/82頁
文件大?。?/td> 447K
代理商: XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
53
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
#4, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0000100
0010100
0100100
0110100
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
RO
0
D6
DMOIE_n
DMO Interrupt Enable:
Writing a “1” to this bit enables DMO
interrupt generation, writing a “0” masks it.
R/W
0
D5
FLSIE_n
FIFO Limit Status Interrupt Enable:
Writing a “1” to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
R/W
0
D4
LCVIE_n
Line Code Violation Interrupt Enable:
Writing a “1” to this bit
enables Line Code Violation interrupt generation, writing a “0”
masks it.
R/W
0
D3
NLCDIE_n
Network Loop-Code Detection Interrupt Enable:
Writing a
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
R/W
0
D2
AISDIE_n
AIS Interrupt Enable:
Writing a “1” to this bit enables Alarm
Indication Signal detection interrupt generation, writing a “0”
masks it.
R/W
0
D1
RLOSIE_n
Receive Loss of Signal Interrupt Enable:
Writing a “1” to this
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
R/W
0
D0
QRPDIE_n
QRSS Pattern Detection Interrupt Enable:
Writing a “1” to
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
R/W
0
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