參數(shù)資料
型號(hào)： XRT83L34IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù)： 63/82頁
文件大?。?/td> 447K
代理商： XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
60
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#12, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0001100
0011100
0101100
0111100
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S5_n -
B0S5_n
Arbitrary Transmit Pulse Shape, Segment 5
The shape of each channel’s transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fifth time segment. B6S5_n-
B0S5_n is in signed magnitude format with B6S5_n as the
sign bit and B0S5_n as the least significant bit (LSB).
R/W
0
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
#13, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0001101
0011101
0101101
0111101
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S6_n -
B0S6_n
Arbitrary Transmit Pulse Shape, Segment 6
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the sixth time segment. B6S6_n-
B0S6_n is in signed magnitude format with B6S6_n as the
sign bit and B0S6_n as the least significant bit (LSB).
R/W
0
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