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參數(shù)資料
| 型號(hào)： | XRT83L34IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128 |
| 文件頁數(shù)： | 67/82頁 |
| 文件大小： | 447K |
| 代理商： | XRT83L34IV |
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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
64
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
#65, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
1000001
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
E1arben
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
R/W
0
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2:
In
Host
mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In
Hardware
mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
R/W
0
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See description of bit D6 for function of this bit.
R/W
0
2048
2048
2048
1544
MCLKE1
kHz
8
16
16
56
8
56
64
64
128
256
256
128
2048
2048
1544
1544
MCLKT1
kHz
1544
X
X
X
1544
X
X
X
X
X
X
X
2048
1544
2048
CLKOUT/
kHz
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
0
1
1
CLKSEL0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
CLKSEL1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
CLKSEL2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1544
2048
X
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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