參數(shù)資料
型號: XRT83L34IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù): 50/82頁
文件大?。?/td> 447K
代理商: XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
47
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0000001
0010001
0100001
0110001
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
RXTSEL_n
Receiver Termination Select:
In
Host
mode, this bit is used
to select between the internal and external line termination
modes for the receiver according to the following table;
R/W
0
D6
TXTSEL_n
Transmit Termination Select:
In
Host
mode, this bit is used
to select between the internal and external line termination
modes for the transmitter according to the following table;
R/W
0
D5
TERSEL1_n
Termination Impedance Select1:
In
Host
mode and in internal termination mode, (TXTSEL = “1”
and RXTSEL = “1”) TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;
In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.
In the internal termination mode, the transmitter output should
be AC coupled to the transformer.
R/W
0
D4
TERSEL0_n
Termination Impedance Select bit 0:
See description of bit D5 for the function of this bit.
R/W
0
RXTSEL
RX Termination
0
1
External
Internal
TXTSEL
TX Termination
0
1
External
Internal
TERSEL1 TERSEL0
0
0
0
1
1
0
1
1
Termination
100
110
75
120
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