參數(shù)資料
型號(hào)： XRT83L34IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁(yè)數(shù)： 51/82頁(yè)
文件大?。?/td> 447K
代理商： XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
48
D3
JASEL1_n
Jitter Attenuator select bit 1:
The JASEL1 and JASEL0 bits
are used to disable or place the jitter attenuator of each chan-
nel independently in the transmit or receive path.
R/W
0
D2
JASEL0_n
Jitter Attenuator select bit 0:
See description of bit D3 for the
function of this bit.
R/W
0
D1
JABW_n
Jitter Attenuator Bandwidth Select:
In E1 mode, set this bit
to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The
FIFO length will be automatically set to 64 bits. Set this bit to
“0” to select 10Hz Bandwidth for the Jitter Attenuator in E1
mode. In T1 mode the Jitter Attenuator Bandwidth is perma-
nently set to 3Hz, and the state of this bit has no effect on the
Bandwidth.
R/W
0
D0
FIFOS_n
FIFO Size Select:
See table of bit D1 above for the function of
this bit.
R/W
0
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
JASEL1
bit D3
JASEL0
bit D2
0
0
0
1
1
0
1
1
JA Path
JA Disabled
JA in Transmit Path
JA in Receive Path
JA in Receive Path
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
0
1
1
0
0
1
1
JABW
bit D1
T1
T1
T1
T1
E1
E1
E1
E1
Mode
32
64
32
64
32
64
64
64
FIFO
Size
3
3
3
3
10
10
1.5
1.5
JA B-W
Hz
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