參數(shù)資料
型號(hào)： XRT83L34IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù)： 30/82頁
文件大?。?/td> 447K
代理商： XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
27
DRIVER FAILURE MONITOR (DMO)
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In
Host
mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware
and
Host
modes on a per channel basis.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In
Hardware
mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In
Host
mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes. Transmit Line Build-Outs for T1 long-haul application are
supported from 0dB to -22.5dB in three 7.5dB steps. The choice of the transmit pulse shape and LBO under
the control of the interface bits are summarized in
Table 5
. For CSU LBO transmit pulse design information,
refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex-E.
N
OTE
:
EQC[4:0] determine the T1/E1 operating mode of the XRT83L34. When EQC4 = “1” and EQC3 = “1”, the XRT83L34
is in the E1 mode, otherwise it is in the T1/J1 mode.
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
E1/T1 M
ODE
& R
ECEIVE
S
ENSITIVITY
T
RANSMIT
LBO
C
ABLE
C
ODING
0
0
0
0
0
T1 Long Haul/36dB
0dB
100
/ TP
B8ZS
0
0
0
0
1
T1 Long Haul/36dB
-7.5dB
100
/ TP
B8ZS
0
0
0
1
0
T1 Long Haul/36dB
-15dB
100
/ TP
B8ZS
0
0
0
1
1
T1 Long Haul/36dB
-22.5dB
100
/ TP
B8ZS
0
0
1
0
0
T1 Long Haul/45dB
0dB
100
/ TP
B8ZS
0
0
1
0
1
T1 Long Haul/45dB
-7.5dB
100
/ TP
B8ZS
0
0
1
1
0
T1 Long Haul/45dB
-15dB
100
/ TP
B8ZS
0
0
1
1
1
T1 Long Haul/45dB
-22.5dB
100
/ TP
B8ZS
0
1
0
0
0
T1 Short Haul/15dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1
0
0
1
T1 Short Haul/15dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
0
1
0
1
0
T1 Short Haul/15dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
0
1
0
1
1
T1 Short Haul/15dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
0
1
1
0
0
T1 Short Haul/15dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
0
1
1
0
1
T1 Short Haul/15dB
Arbitrary Pulse
100
/ TP
B8ZS
相關(guān)PDF資料
PDF描述
XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314_0610 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38_0609 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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