參數(shù)資料
型號(hào)： XRT83L34IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù)： 5/82頁
文件大小： 447K
代理商： XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ............................................ 1
Figure 2 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode) ................................... 2
F
EATURES
.................................................................................................................................................... 2
ORDERING INFORMATION ...................................................................................................................... 3
Figure 3 Pin Out of the XRT83L34 .................................................................................................... 4
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTION BY FUNCTION ................................................................................... 5
R
ECEIVE
S
ECTIONS
...................................................................................................................................... 5
T
RANSMITTER
S
ECTIONS
.............................................................................................................................. 7
M
ICROPROCESSOR
I
NTERFACE
...................................................................................................................... 9
J
ITTER
A
TTENUATOR
.................................................................................................................................. 12
C
LOCK
S
YNTHESIZER
.................................................................................................................................. 13
A
LARM
F
UNCTION
//R
EDUNDANCY
S
UPPORT
................................................................................................. 14
P
OWER
AND
GROUND
................................................................................................................................. 18
FUNCTIONAL DESCRIPTION ......................................................................................... 19
M
ASTER
C
LOCK
G
ENERATOR
...................................................................................................................... 19
Figure 4. Two Input Clock Source .................................................................................................. 19
Figure 5. One Input Clock Source .................................................................................................. 19
RECEIVER ........................................................................................................................ 20
R
ECEIVER
I
NPUT
......................................................................................................................................... 20
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
............................................................................................... 20
R
ECEIVE
M
ONITOR
M
ODE
........................................................................................................................... 21
R
ECEIVER
L
OSS
OF
S
IGNAL
(RLOS) ........................................................................................................... 21
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 21
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 22
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ............... 22
R
ECEIVE
HDB3/B8ZS D
ECODER
................................................................................................................ 23
R
ECOVERED
C
LOCK
(RCLK) S
AMPLING
E
DGE
............................................................................................ 23
Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 23
Figure 10. Receive Clock and Output Data Timing ....................................................................... 23
J
ITTER
A
TTENUATOR
.................................................................................................................................. 24
G
APPED
C
LOCK
(JA M
UST
BE
E
NABLED
IN
THE
T
RANSMIT
P
ATH
) ................................................................. 24
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
........................................ 24
A
RBITRARY
P
ULSE
G
ENERATOR
FOR
T1
AND
E
1 .......................................................................................... 25
TRANSMITTER ................................................................................................................. 25
D
IGITAL
D
ATA
F
ORMAT
............................................................................................................................... 25
T
RANSMIT
C
LOCK
(TCLK) S
AMPLING
E
DGE
................................................................................................ 25
Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 25
T
RANSMIT
HDB3/B8ZS E
NCODER
.............................................................................................................. 26
Figure 12. Transmit Clock and Input Data Timing ........................................................................ 26
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
........................................................................................... 26
T
ABLE
4: E
XAMPLES
OF
B8ZS E
NCODING
........................................................................................... 26
D
RIVER
F
AILURE
M
ONITOR
(DMO) .............................................................................................................. 27
T
RANSMIT
P
ULSE
S
HAPER
& L
INE
B
UILD
O
UT
(LBO)
CIRCUIT
...................................................................... 27
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
........................... 27
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 29
RECEIVER (C
HANNELS
0 - 3) ................................................................................................................... 29
Internal Receive Termination Mode .......................................................................................................... 29
T
ABLE
6: R
ECEIVE
T
ERMINATION
C
ONTROL
.......................................................................................... 29
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