參數(shù)資料
型號(hào)： XRT83L34IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù)： 12/82頁
文件大?。?/td> 447K
代理商： XRT83L34IV
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
9
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
HW_HOST
68
I
Mode Control Input
This pin selects
Hardware
or
Host mode
. Leave this pin unconnected or tie
“High” to select
Hardware mode
.
For
Host mode
, this pin must be tied “Low”.
N
OTE
:
Internally pulled “High” with a 50k
resistor.
WR_R/W
TAOS_0
69
69
I
Write Input (Read/Write)
-
Host mode
Intel bus timing:
A “Low” pulse on WR selects a write operation when CS
pin is “Low”.
Motorola bus timing:
A “High” pulse on R/W selects a read operation and a
“Low” pulse on R/W selects a write operation when CS is “Low”.
Transmit All “Ones” Channel_0 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 8.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
RD_DS
TAOS_1
70
70
I
Read Input (Data Strobe) - Host Mode
Intel bus timing:
A “Low” pulse on RD selects a read operation when the CS
pin is “Low”.
Motorola bus timing:
A “Low” pulse on DS indicates a read or write opera-
tion when the CS pin is “Low”.
Transmit All “Ones” Channel_1 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 8.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
ALE_AS
TAOS_2
71
71
I
Address Latch Input (Address Strobe) - Host Mode
Intel bus timing:
The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing:
The address inputs are latched into the internal regis-
ter on the falling edge of AS.
Transmit All “Ones” Channel_2 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 8.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
CS
TAOS_3
72
72
I
Chip Select Input - Host Mode
This signal must be “Low” in order to access the parallel port.
Transmit All “Ones” Channel_3 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 8.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
RDY_DTACK
RXMUTE
73
73
O
I
Ready Output (Data Transfer Acknowledge Output) - Host Mode
Intel bus timing
: RDY is asserted “High” to indicate the device has com-
pleted a read or write operation.
Motorola bus timing:
DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.
Receive Muting - Hardware mode
See “Receive Muting - Hardware mode” on page 6.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
相關(guān)PDF資料
PDF描述
XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314_0610 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83L38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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