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參數(shù)資料
| 型號： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
Publication Release Date: April 11, 2003
- 17 -
Revision A4
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate various failure conditions (see Table 6). By
allowing system software to reset these bits, several operations (such as cumulatively erasing multiple
blocks or writing several words/bytes in sequence) may be performed. The status register may be
polled to determine if an error occurred during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions
independently of the applied VPP voltage. #RESET can be VIH. This command is not functional during
block erase or word/byte write suspend modes.
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm. This command sequence requires appropriate
sequencing and an address within the block to be erased (erase changes all block data to
FFFFH/FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to
the system). After the two-cycle block erase sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU can detect block erase completion by
analyzing the output data of the RY/#BY pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command sequence will result in both status register bits
SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VDD = 2.7V to 3.6V
and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If
block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase for
boot blocks requires that #WP = VIH and the corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding block lock-bit. If block erase is attempted
when the excepting above conditions, SR.1 and SR.5 will be set to "1".
Full Chip Erase Command
This command followed by a confirm command erases all of the unlocked blocks. A full chip erase
setup (30H) is first written, followed by a full chip erase confirm (D0H). After a confirm command is
written, device erases the all unlocked blocks block by block. This command sequence requires
appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip erase sequence is written, the device
automatically outputs status register data when can be read (see Figure 7). The CPU can detect full
chip erase completion by analyzing the output data of the RY/#BY pin or status register bit SR.7.
When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is
detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued. If error is detected on a
block during full chip erase operation, WSM stops erasing. Full chip erase operation start from lower
address block, finish the higher address block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VDD = 2.7V to
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