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參數(shù)資料
| 型號： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大小： | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
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When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up, followed by execution, ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur only when VDD = 2.7V to 3.6V and VPP = VPPH1/2.
In the absence of this high voltage, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is
attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail.
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. If the permanent
lock-bit is not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the
permanent lock-bit is set, block lock-bits cannot be cleared. Refer to Table 5 for a summary of
hardware and software write protection options.
Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the device automatically outputs status register
data when read (refer to Figure 12). The CPU can detect completion of the clear block lock-bits event
by reading the RY/#BY Pin output or status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur
when VDD = 2.7V to 3.6V and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while
VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits
content are protected against alteration. A successful clear block lock-bits operation requires that the
permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be
set to "1" and the operation will fail.
If a clear block lock-bits operation is aborted due to VPP or VDD transitioning out of valid range or
#RESET active transition, block lock-bit values are left in an undetermined state. A repeat of clear
block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent
lock-bit is set, it cannot be cleared.
OTP Program Command
OTP program is executed by a two-cycle command sequence. OTP program command(C0H) is
written, followed by a second write cycle that specifies the address and data (latched on the rising
edge of #WE). The WSM then takes over, controlling the OTP program and program verify algorithms
internally. After the OTP program command sequence is completed, the device automatically outputs
status register data when read (see Figure 13). The CPU can detect the completion of the OTP
program by analyzing the output data of the RY/#BY pin or status register bit SR.7.
When OTP program is completed, status register bit SR.4 should be checked. If OTP program error is
detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s
that do not successfully program to "0"s. The CUI remains in read status register mode until it receives
other commands.
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