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參數(shù)資料
| 型號： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
Publication Release Date: April 11, 2003
- 21 -
Revision A4
Reliable OTP program can be executed only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the
absence of this voltage, memory contents are protected against OTP programs. If OTP program is
attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 is set to "1". If OTP write is attempted
when the OTP Lock-bit is set, SR.1 and SR.4 is set to "1".
Block Locking by the #WP
This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure while other blocks are programmed or erased as
necessary.
The lockable two boot blocks are locked when #WP = VIL; any program or erase operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the top
two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable.
If #WP is VIH and block lockbit is not set, boot block can be programmed or erased normally (unless
VPP is below VPPLK). The #WP is valid only for two boot blocks, other blocks are not affected.
Table 5. Write Protection Alternatives
OPERATION
VPP
#RESET
PERMANENT
LOCK-BIT
BLOCK
LOCK-BIT
#WP
EFFECT
≤
VPPLK
X
All Blocks Locked.
VIL
X
All Blocks Locked.
VIL
2 Boot Blocks Locked.
0
VIH Block Erase and Word/Byte Write Enabled.
VIL
Block Erase and Word/Byte Write Disabled.
Block Erase or
Word/Byte
Write
>
VPPLK
VIH
X
1
VIH Block Erase and Word/Byte Write Disabled.
≤
VPPLK
X
All Blocks Locked.
VIL
X
All Blocks Locked.
VIL
All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are NOT
Erased.
Full Chip
Erase
>
VPPLK
VIH
X
VIH
All Unlocked Blocks are Erased.
Locked Blocks are NOT Erased.
≤
VPPLK
X
Set Block Lock-Bit Disabled.
VIL
X
Set Block Lock-Bit Disabled.
0
X
Set Block Lock-Bit. Enabled.
Set Block
Lock-Bit
>
VPPLK
VIH
1
X
Set Block Lock-Bit Disabled.
≤
VPPLK
X
Clear Block Lock-Bits Disabled.
VIL
X
Clear Block Lock-Bits Disabled.
0
X
Clear Block Lock-Bits Enabled.
Clear Block
Lock-Bits
>
VPPLK
VIH
1
X
Clear Block Lock-Bits Disabled.
≤
VPPLK
X
Set Permanent Lock-Bit Disabled.
VIL
X
Set Permanent Lock-Bit Disabled.
Set
Permanent
Lock-Bit
>
VPPLK
VIH
X
Set Permanent Lock-Bit Enabled.
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