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參數(shù)資料
| 型號(hào)： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁(yè)數(shù)： | 21/48頁(yè) |
| 文件大?。?/td> | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
- 28 -
Bus Operation
Command
Comments
Write
Read Status
Register
Data = 70H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write
Set
Block/Permanent
Lock-Bit Setup
Data = 60H
Addr = X
Write
Set Block or
Permanent
Lock-Bit Confirm
Data = 01H (Block),
F1H (Permanent)
Addr = Block
Address(Block),
Device Address (Permanent)
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Start
Write 70H
SR.7=
Write 60H
Read Status
Register
SR.7=
Full Status
Check if Desired
Set Lock-Bit
Complete
Read Status
Register
Write 01H/F1H
1
0
1
0
Block/Device Address
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
SR.1=
SR.4,5=
SR.4=
Set Lock-Bit Successfully
0
1
Vpp Range Error
Device Protect Error
Command Sequence
Set Lock-Bit Error
Error
Bus Operation
Command
Comments
Standby
Check SR.3
1 =
VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Permanent Lock-Bit is Set
(Set Block Lock-Bit Operation)
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.4
1 = Set Lock-Bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits are
set before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 11. Set Block and Permanent Lock-Bit Flowchart
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