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參數(shù)資料
| 型號(hào)： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁(yè)數(shù)： | 36/48頁(yè) |
| 文件大?。?/td> | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
Publication Release Date: April 11, 2003
- 41 -
Revision A4
Alternative #CE - Controlled Writes(1)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYM.
MIN.
MAX.
UNIT
Write Cycle Time
tAVAV
90
nS
#RESET High Recovery to #CE Going Low (note 2)
tPHEL
1
S
#WE Setup to #CE Going Low
tWLEL
0
nS
#CE Pulse Width
tELEH
65
nS
#WP VIH Setup to #CE Going High (note 2)
tSHEH
100
nS
VPP Setup to #CE Going High (note 2)
tVPEH
100
nS
Address Setup to #CE Going High (note 3)
tAVEH
50
nS
Data Setup to #CE Going High (note 3)
tDVEH
50
nS
Data Hold from #CE High
tEHDX
0
nS
Address Hold from #CE High
tEHAX
0
nS
#WE Hold from #CE High
tEHWH
0
nS
#CE Pulse Width High
tEHEL
25
nS
#CE High to RY/#BY Going Low or SR.7 Going "0"
tEHRL
100
nS
Write Recovery before Read
tEHGL
0
nS
VPP Hold from Valid SRD, RY/#BY High Z (note 2, 4)
tQVVL
0
nS
#WP VIH Hold from Valid SRD, RY/#BY High Z (note2, 4)
tQVSL
0
nS
#BYTE Setup to #CE Going High (note5)
tFVEH
50
nS
#BYTE Hold from #CE High (note5)
tEHFV
90
nS
Notes:
1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE
times should be measured relative to the #CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration
success (SR.1/3/4/5 = 0).
5. If #BYTE switch during reading cycle, exist the regulations separately.
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