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參數(shù)資料
| 型號： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大小： | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
Publication Release Date: April 11, 2003
- 39 -
Revision A4
AC Characteristics - Write Operations(1)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYM.
MIN.
MAX.
UNIT
Write Cycle Time
tAVAV
90
nS
#RESET High Recovery to #WE Going Low (note 2)
tPHWL
1
S
#CE Setup to #WE Going Low
tELWL
10
nS
#WE Pulse Width
tWLWH
50
nS
#WP VIH Setup to #WE Going High (note 2)
tSHWH
100
nS
VPP Setup to #WE Going High (note 2)
tVPWH
100
nS
Address Setup to #WE Going High (note 3)
tAVWH
50
nS
Data Setup to #WE Going High (note 3)
tDVWH
50
nS
Data Hold from #WE High
tWHDX
0
nS
Address Hold from #WE High
tWHAX
0
nS
#CE Hold from #WE High
tWHEH
10
nS
#WE Pulse Width High
tWHWL
30
nS
#WE High to RY/#BY Going Low or SR.7 Going "0"
tWHRL
100
nS
Write Recovery before Read
tWHGL
0
nS
VPP Hold from Valid SRD, RY/#BY High Z (note 2, 4)
tQVVL
0
nS
#WP VIH Hold from Valid SRD, RY/#BY High Z (note 2, 4)
tQVSL
0
nS
#BYTE Setup to #WE Going High (note 5)
tFVWH
50
nS
#BYTE Hold from #WE High (note 5)
tWHFV
90
nS
Notes:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are the
same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration
success (SR.1/3/4/5 = 0).
5. If #BYTE switch during reading cycle, exist the regulations separately.
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