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參數資料
| 型號： | W28J320TT90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數： | 26/48頁 |
| 文件大?。?/td> | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
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lock-bit configuration, RY/#BY will remain low until the reset operation is complete. Then, the
operation will abort and the device will enter reset mode. The aborted operation may leave data
partially altered. Therefore, the command sequence must be repeated after normal operation is
restored. Device power-off or #RESET transitions to VIL clear the status register.
The CUI latches commands issued by system software and is not altered by VPP or #CE transitions or
WSM actions. Its state is read array mode upon power-up, after exit from reset mode or after VDD
transitions below VLKO.
Power-Up/Down Protection
The device is designed to offer protection against accidental block erase, full chip erase, word/byte
write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to
which power supply (VPP or VDD) powers-up first. Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for VDD voltages above VLKO when VPP is active.
Since both #WE and #CE must be low for a command write, driving either to VIH will inhibit writes. The
CUI’s two-step command sequence architecture provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled
while #RESET = VIL regardless of its control inputs state.
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s non-
volatility increases usable battery life because data is retained when system power is removed.
Data Protection Method
On some systems, noise having a level exceeding the limit dictated in the specification may be
generated under specific operating conditions. Such noise, when induced onto #WE signal or power
supply, may be interpreted as false commands, causing undesired memory updating. To protect the
data stored in the flash memory against undesired overwriting, systems operating with the flash
memory should have the following write protect designs, as appropriate:
1) Protecting data in specific block
When a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against
overwriting. By setting a #WP low, only the 2 boot blocks can be protected against overwriting. By
using this feature, the flash memory space can be divided into the program section (locked
section) and data section (unlocked section). The permanent lock bit can be used to prevent false
block bit setting. For further information on setting/resetting lock-bit, refer to the specification.
2) Data protection through VPP
When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is
disabled. All blocks are locked and the data in the blocks are completely write protected. For the
lockout voltage, refer to the specification.
3) Data protection through #RESET
When the #RESET is kept low during read mode, the flash memory will be in reset mode, write
protecting all blocks. When the #RESET is kept low during power up and power down sequence
such as voltage transition, write operation on the flash memory is disabled, write protecting all
blocks. For the details of #RESET control, refer to the specification.
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