參數(shù)資料
型號: W25Q64BVSSIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 8M X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.208 INCH, GREEN, PLASTIC, SOIC-8
文件頁數(shù): 42/61頁
文件大?。?/td> 1726K
代理商: W25Q64BVSSIG
W25Q64BV
Publication Release Date: July 08, 2010
- 47 -
Revision E
11.2.29 Continuous Read Mode Reset (FFh or FFFFh)
For Fast Read Dual/Quad I/O operations, “Continuous Read Mode” Bits (M7-0) are implemented to
further reduce instruction overhead. By setting the (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O
operation does not require the BBh/EBh instruction code (See 11.2.12 Fast Read Dual I/O and 11.2.13
Fast Read Quad I/O for detail descriptions).
If the system controller is Reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the W25Q64BV. However, as with most SPI Serial Flash
memories, the W25Q64BV does not have a hardware Reset pin, so if Continuous Read Mode bits are set
to “Ax” hex, the W25Q64BV will not recognize any standard SPI instructions. To address this possibility, it
is recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a
system Reset. Doing so will release the Continuous Read Mode from the “Ax” hex state and allow
Standard SPI instructions to be recognized. The Continuous Read Mode Reset instruction is shown in
figure 30.
/CS
Mode Bit Reset
for Dual I/O
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
Mode Bit Reset
for Quad I/O
FFh
Don’t Care
CLK
IO
0
IO
1
IO
2
/CS
Mode Bit Reset
for Dual I/O
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
Mode Bit Reset
for Quad I/O
FFh
Don’t Care
IO
3
Don’t Care
IO
3
CLK
IO
0
IO
1
IO
2
Figure 30. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
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