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參數(shù)資料
| 型號(hào)： | W25Q64BVSSIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 15/61頁 |
| 文件大小： | 1726K |
| 代理商： | W25Q64BVSSIG |
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W25Q64BV
- 22 -
11.2.7 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low,
sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 7.
The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status
Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to. All other Status Register
bit locations are read-only and will not be affected by the Write Status Register instruction.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not
done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock
(compatible with the 25X series) the QE and SRP1 bits will be cleared to 0. After /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0) to be
set for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table and description). The Write Status
Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to be set. Those bits are
used in conjunction with the Write Protect (/WP) pin, Lock out or OTP features to disable writes to the
status register. Please refer to 11.1.6 for detailed descriptions regarding Status Register protection
methods. Factory default for all status Register bits are 0.
Figure 7. Write Status Register Instruction Sequence Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q64BVSSIGTR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 64M-BIT, 4KB UNIFORM |
| W25Q64BVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64BVZEIG | 功能描述:IC SPI FLASH 64MBIT 8WSON RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:SpiFlash® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W25Q64BVZEIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CV | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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