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參數(shù)資料
| 型號： | W25Q64BVSSIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 20/61頁 |
| 文件大小： | 1726K |
| 代理商： | W25Q64BVSSIG |
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W25Q64BV
Publication Release Date: July 08, 2010
- 27 -
Revision E
11.2.12 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications. To ensure optimum performance the
High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the Fast Read Dual I/O
Instruction.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Fast Read Dual I/O instruction
(after /CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value other than
“Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code,
thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset
(M7-0) before issuing normal instructions (See 11.2.29 for detailed descriptions).
Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)
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| WF2M32S-100HM | 8M X 8 FLASH 5V PROM MODULE, 100 ns, CHIP66 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q64BVSSIGTR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 64M-BIT, 4KB UNIFORM |
| W25Q64BVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64BVZEIG | 功能描述:IC SPI FLASH 64MBIT 8WSON RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W25Q64BVZEIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CV | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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